| Message ID | 20171022024641.28478-4-shorne@gmail.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | None | expand |
On Sun, Oct 22, 2017 at 11:46:41AM +0900, Stafford Horne wrote: > Add devicetree binding documentation for the OpenRISC platform > opencores,or1ksim. This is the main OpenRISC reference platform > supporting multiple FPGA SoC's. > > This format is based on some of the mips binding docs as we have > similar requirements. > > Also, update maintainers so openrisc related binding changes are visible > to the openrisc team. Your subject is wrong because this is not a dts patch. Use "dt-bindings: openrisc: ..." > > Suggested-by: Pavel Machek <pavel@ucw.cz> > Signed-off-by: Stafford Horne <shorne@gmail.com> > --- > .../bindings/openrisc/opencores/or1ksim.txt | 39 ++++++++++++++++++++++ > MAINTAINERS | 1 + > 2 files changed, 40 insertions(+) > create mode 100644 Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt Otherwise, Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Oct 26, 2017 at 10:18:33PM -0500, Rob Herring wrote: > On Sun, Oct 22, 2017 at 11:46:41AM +0900, Stafford Horne wrote: > > Add devicetree binding documentation for the OpenRISC platform > > opencores,or1ksim. This is the main OpenRISC reference platform > > supporting multiple FPGA SoC's. > > > > This format is based on some of the mips binding docs as we have > > similar requirements. > > > > Also, update maintainers so openrisc related binding changes are visible > > to the openrisc team. > > Your subject is wrong because this is not a dts patch. Use > "dt-bindings: openrisc: ..." I will fix that, I should have noticed. > > > > Suggested-by: Pavel Machek <pavel@ucw.cz> > > Signed-off-by: Stafford Horne <shorne@gmail.com> > > --- > > .../bindings/openrisc/opencores/or1ksim.txt | 39 ++++++++++++++++++++++ > > MAINTAINERS | 1 + > > 2 files changed, 40 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt > > Otherwise, > > Acked-by: Rob Herring <robh@kernel.org> Thank you. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sun, Oct 22, 2017 at 11:46:41AM +0900, Stafford Horne wrote: > Add devicetree binding documentation for the OpenRISC platform > opencores,or1ksim. This is the main OpenRISC reference platform > supporting multiple FPGA SoC's. > > This format is based on some of the mips binding docs as we have > similar requirements. > > Also, update maintainers so openrisc related binding changes are visible > to the openrisc team. > [..] > diff --git a/MAINTAINERS b/MAINTAINERS > index a57d13cb414d..71e4f6762196 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10008,6 +10008,7 @@ T: git git://github.com/openrisc/linux.git > L: openrisc@lists.librecores.org > W: http://openrisc.io > S: Maintained > +F; Documentation/devicetree/bindings/openrisc/ FYI, I found this typo (; vs :) which I have fixed and am pushing to next. > F: Documentation/openrisc/ > F: arch/openrisc/ > F: drivers/irqchip/irq-or1k-* > -- > 2.13.6 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt new file mode 100644 index 000000000000..4950c794ecbb --- /dev/null +++ b/Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt @@ -0,0 +1,39 @@ +OpenRISC Generic SoC +==================== + +Boards and FPGA SoC's which support the OpenRISC standard platform. The +platform essentially follows the conventions of the OpenRISC architecture +specification, however some aspects, such as the boot protocol have been defined +by the Linux port. + +Required properties +------------------- + - compatible: Must include "opencores,or1ksim" + +CPU nodes: +---------- +A "cpus" node is required. Required properties: + - #address-cells: Must be 1. + - #size-cells: Must be 0. +A CPU sub-node is also required for at least CPU 0. Since the topology may +be probed via CPS, it is not necessary to specify secondary CPUs. Required +properties: + - compatible: Must be "opencores,or1200-rtlsvn481". + - reg: CPU number. + - clock-frequency: The CPU clock frequency in Hz. +Example: + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + +Boot protocol +------------- +The bootloader may pass the following arguments to the kernel: + - r3: address of a flattened device-tree blob or 0x0. diff --git a/MAINTAINERS b/MAINTAINERS index a57d13cb414d..71e4f6762196 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10008,6 +10008,7 @@ T: git git://github.com/openrisc/linux.git L: openrisc@lists.librecores.org W: http://openrisc.io S: Maintained +F; Documentation/devicetree/bindings/openrisc/ F: Documentation/openrisc/ F: arch/openrisc/ F: drivers/irqchip/irq-or1k-*
Add devicetree binding documentation for the OpenRISC platform opencores,or1ksim. This is the main OpenRISC reference platform supporting multiple FPGA SoC's. This format is based on some of the mips binding docs as we have similar requirements. Also, update maintainers so openrisc related binding changes are visible to the openrisc team. Suggested-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Stafford Horne <shorne@gmail.com> --- .../bindings/openrisc/opencores/or1ksim.txt | 39 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/openrisc/opencores/or1ksim.txt