From patchwork Wed Jun 21 13:29:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 778884 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wt5Ct01J9z9s78 for ; Wed, 21 Jun 2017 23:29:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751656AbdFUN31 (ORCPT ); Wed, 21 Jun 2017 09:29:27 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:33364 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751148AbdFUN3Z (ORCPT ); Wed, 21 Jun 2017 09:29:25 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id CBC8C209B9; Wed, 21 Jun 2017 15:29:23 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id A3EA4209B4; Wed, 21 Jun 2017 15:29:23 +0200 (CEST) From: Thomas Petazzoni To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-arm-kernel@lists.infradead.org, Nadav Haklai , Hanna Hawa , Yehuda Yitschak , Antoine Tenart , =?UTF-8?q?Miqu=C3=A8l=20Raynal?= , Thomas Petazzoni Subject: [PATCH v5 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP Date: Wed, 21 Jun 2017 15:29:12 +0200 Message-Id: <20170621132917.14187-2-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170621132917.14187-1-thomas.petazzoni@free-electrons.com> References: <20170621132917.14187-1-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni Acked-by: Rob Herring --- .../bindings/interrupt-controller/marvell,gicp.txt | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt new file mode 100644 index 0000000..64a00ce --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt @@ -0,0 +1,27 @@ +Marvell GICP Controller +----------------------- + +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI +interrupts by doing a memory transaction. It is used by the ICU +located in the Marvell CP110 to turn wired interrupts inside the CP +into GIC SPI interrupts. + +Required properties: + +- compatible: Must be "marvell,ap806-gicp" + +- reg: Must be the address and size of the GICP SPI registers + +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available + for this GICP + +- msi-controller: indicates that this is an MSI controller + +Example: + +gicp_spi: gicp-spi@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; +};