From patchwork Wed Jun 21 12:04:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 778801 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wt3Kj4d2Rz9ryr for ; Wed, 21 Jun 2017 22:04:25 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Jl4pqFW4"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751962AbdFUMEX (ORCPT ); Wed, 21 Jun 2017 08:04:23 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:35984 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751938AbdFUMEU (ORCPT ); Wed, 21 Jun 2017 08:04:20 -0400 Received: by mail-qk0-f193.google.com with SMTP id r62so15065829qkf.3; Wed, 21 Jun 2017 05:04:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=80iXfB8WNVsTIcvzMg5zJt7Va76KB8rq9XzJf49ni6k=; b=Jl4pqFW46rLOfbsMZsCxAxpcmAZZlt25LR6eSmled2i22PDNKVKlMiNOPIhB+ZDqJI pWAM6adci8qzqlVsOArBIkTJvs0iSEhNDYERFX6+/Ns5blC6EW5oocs2LCUkmv8934bW 77jERYEC/jNYXVhsSGGuoWTvPS5RFZYwrLxCp7u8JkDUVftMllTm6dutu8tWDwwLhGWO A0ZhCKFTCXv4AKNvphW4BVF1XXqREfe536eUKNEum8eNKlXjZrpBe/A5ImOfpJf6NTfy exqHuXXxTWieTuqhexYyNSa1kiJvnPFW5RUU3bhIHpsABDlEHV1+F0t+sqgh0tb2yfci ZHHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=80iXfB8WNVsTIcvzMg5zJt7Va76KB8rq9XzJf49ni6k=; b=Mwfwoj8tHMRtEqi88vF/R9KF+quu1Ss9uf/K5JXcG+jmzxG5iMudAG+a7To9V/mvv2 6DT+cFc6gTHsdaY8w4ZhbUFIxKUcswuP//Csi13x/fZ/UOzEB8slabb/3NMv4TwQpgan E0X68f2UggVRosbmqsxN9HqaiVJoruSoHNdVdmp6uXa5IljAmEDv7BCwmpigRWp8NvM0 0GiEi+NnAtxhzNItYge7FfqO5aWboCLvNi56yKftikd4RhkB6uEvqB7GI/Ods+iZikVN ZIE/2QRmID+CoMieJYmg9G0OJWOrZHgfolRSl8TcfnWIPkgu5YLUm9kcdAGd+bgxBir6 t0bQ== X-Gm-Message-State: AKS2vOyM8S7kJpQWmvi5+B+9PKVgKYlhPiH6elRefqqcPXwKiipgwvC4 LqzlsGFiIfQTVXJubQw= X-Received: by 10.55.122.133 with SMTP id v127mr40435009qkc.129.1498046658861; Wed, 21 Jun 2017 05:04:18 -0700 (PDT) Received: from localhost ([144.121.20.162]) by smtp.gmail.com with ESMTPSA id w8sm591977qtb.53.2017.06.21.05.04.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Jun 2017 05:04:17 -0700 (PDT) From: Rob Clark To: iommu@lists.linux-foundation.org Cc: linux-arm-msm@vger.kernel.org, Robin Murphy , Rob Herring , Will Deacon , Sricharan , Archit Taneja , Mark Rutland , Stanimir Varbanov , Rob Clark , devicetree@vger.kernel.org Subject: [RESEND PATCH 1/4] Docs: dt: document qcom iommu bindings Date: Wed, 21 Jun 2017 08:04:03 -0400 Message-Id: <20170621120406.2053-2-robdclark@gmail.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170621120406.2053-1-robdclark@gmail.com> References: <20170621120406.2053-1-robdclark@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Clark Reviewed-by: Rob Herring --- .../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt new file mode 100644 index 0000000..b2641ce --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -0,0 +1,121 @@ +* QCOM IOMMU v1 Implementation + +Qualcomm "B" family devices which are not compatible with arm-smmu have +a similar looking IOMMU but without access to the global register space, +and optionally requiring additional configuration to route context irqs +to non-secure vs secure interrupt line. + +** Required properties: + +- compatible : Should be one of: + + "qcom,msm8916-iommu" + + Followed by "qcom,msm-iommu-v1". + +- clock-names : Should be a pair of "iface" (required for IOMMUs + register group access) and "bus" (required for + the IOMMUs underlying bus access). + +- clocks : Phandles for respective clocks described by + clock-names. + +- #address-cells : must be 1. + +- #size-cells : must be 1. + +- #iommu-cells : Must be 1. Index identifies the context-bank #. + +- ranges : Base address and size of the iommu context banks. + +- qcom,iommu-secure-id : secure-id. + +- List of sub-nodes, one per translation context bank. Each sub-node + has the following required properties: + + - compatible : Should be one of: + - "qcom,msm-iommu-v1-ns" : non-secure context bank + - "qcom,msm-iommu-v1-sec" : secure context bank + - reg : Base address and size of context bank within the iommu + - interrupts : The context fault irq. + +** Optional properties: + +- reg : Base address and size of the SMMU local base, should + be only specified if the iommu requires configuration + for routing of context bank irq's to secure vs non- + secure lines. (Ie. if the iommu contains secure + context banks) + + +** Examples: + + apps_iommu: iommu@1e20000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@2000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + ... + + venus: video-codec@1d00000 { + ... + iommus = <&apps_iommu 5>; + }; + + mdp: mdp@1a01000 { + ... + iommus = <&apps_iommu 4>; + }; + + gpu@01c00000 { + ... + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + };