From patchwork Fri May 26 03:32:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 767219 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wYsCg25jJz9s8V for ; Fri, 26 May 2017 13:33:03 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sTUrmIEk"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939764AbdEZDcm (ORCPT ); Thu, 25 May 2017 23:32:42 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:34591 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S939762AbdEZDch (ORCPT ); Thu, 25 May 2017 23:32:37 -0400 Received: by mail-pf0-f196.google.com with SMTP id w69so43033029pfk.1; Thu, 25 May 2017 20:32:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=EX9HUgqPgi5/ufaPta6uyFnHaZMjZzXwtI7CdSCBooE=; b=sTUrmIEk3QsKwF4hZ31CC2x1XlACYhv1VZcaLGriytzfa7BNtT4VgUtQ6thhA/6l6z DLqgIplT14wXpZW8gDI3mjAEVx98pFZX65BCPudP+RM9kNTh7BaHdJiFKkC7Qw4ZF8lV HB5MdS1f0b4ZTjxiSruKpgXsD/BXcJtiGWZ5gf1elO4D/Vo/o38DC+oHnP28piR9uafF 1xIMSkef19rwNvUH66NqTv14AJFU8WW6Y70Uh8q5deM4apH2yUND0VZ9w0x7UF1QuOtY QiG3BJxwZxwisVzuw5cMwN4B6B14SYyrsCMwv5eOn8l7sA7k41IX2MjJeWfVB5bCQE9q EH6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=EX9HUgqPgi5/ufaPta6uyFnHaZMjZzXwtI7CdSCBooE=; b=XQo4jNpBfjwrTf3Y4htKYFdn9qWAYkOXMgoFRcN8Oz2mk4VJcIuyjSar1DrDwoZGlo UI3iWJJToQ9+BDrkIhSTyULDTG7pL/lEmmquXYjxY3bk7NpPqWYW8KrndG63IKkxXRcI PCKvaFhw8dilz9IYQBKUH9VCvNX0iWKIAjsut65nWhUAKxggJz/UGzwxNn5HmI71qod+ iKe3K7l7LIrDnbNpXermXEYK1Yd3VQb2cHGFS4Xen7QvfPLuNC5k8+A1/nw1dmHDCReg BaTU+OHWUSGdjL82r4mZ8ZlBXcs+4uJIL48D6SKwV6J2U4tlZtTGb88d3ntkRB4jcm7C S/IA== X-Gm-Message-State: AODbwcBtB6082vF/cojkOGvI89s0kWFZQRiokZ44tV4lU6jIN6tiUjyw oworj+0q5x71ZA== X-Received: by 10.99.97.68 with SMTP id v65mr49738756pgb.76.1495769556910; Thu, 25 May 2017 20:32:36 -0700 (PDT) Received: from aurora.jms.id.au (bh02i525f01.au.ibm.com. [202.81.18.30]) by smtp.gmail.com with ESMTPSA id c23sm16290636pfh.131.2017.05.25.20.32.31 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 25 May 2017 20:32:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 26 May 2017 13:32:27 +1000 From: Joel Stanley To: Philipp Zabel , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Andrew Jeffery Subject: [PATCH 1/2] dt-bindings: reset: Add bindings for basic reset controller Date: Fri, 26 May 2017 13:32:13 +1000 Message-Id: <20170526033214.8081-2-joel@jms.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170526033214.8081-1-joel@jms.id.au> References: <20170526033214.8081-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the bindings documentation for a basic single-register reset controller. The bindings describe a single 32-bit register that contains up to 32 reset lines, each deasserted by clearing the appropriate bit in the register. Signed-off-by: Joel Stanley --- .../devicetree/bindings/reset/reset-basic.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/reset-basic.txt diff --git a/Documentation/devicetree/bindings/reset/reset-basic.txt b/Documentation/devicetree/bindings/reset/reset-basic.txt new file mode 100644 index 000000000000..7341e04e7904 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/reset-basic.txt @@ -0,0 +1,31 @@ +Basic single-register reset controller +====================================== + +This describes a generic reset controller where the reset lines are controlled +by single bits within a 32-bit memory location. The memory location is assumed +to be part of a syscon regmap. + +Reset controller required properties: + - compatible: should be "reset-basic" + - #reset-cells: must be set to 1 + - reg: reset register location within regmap + +Device node required properties: + - resets phandle + - bit number, counting from zero, for the desired reset line. Max is 31. + +Example: + +syscon { + compatible = "syscon"; + + uart_rest: rest@0c { + compatible = "reset-basic"; + #reset-cells = <1>; + reg = <0x0c>; + }; +} + +&uart { + resets = <&uart_rest 0x04>; +}