From patchwork Thu May 4 13:34:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 758569 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wJbcc6pkkz9s1h for ; Thu, 4 May 2017 23:35:12 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="SlP4KbLv"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754121AbdEDNfK (ORCPT ); Thu, 4 May 2017 09:35:10 -0400 Received: from mail-qk0-f195.google.com ([209.85.220.195]:36326 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752948AbdEDNfJ (ORCPT ); Thu, 4 May 2017 09:35:09 -0400 Received: by mail-qk0-f195.google.com with SMTP id y128so602750qka.3; Thu, 04 May 2017 06:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l9Ts5DM981lqeJ00fftKEbTxkjTHmKPfGAXmwGATixo=; b=SlP4KbLv/koxsiqnbM11MgmTsnEe6X/YNKdp33A0flysGE28DDw+Z+toGahi5oFbxG 4leunz9+oXXgMVQzA6as7iChOahvf/5LL3OsSS6xbfiNSNkfgD2alY3/r1oZCkZaYBJr EApFFqcgosPjP9uH0AU3fxG8y1wWuMgB1Xb7Xx7yGC3EnMUvxllvFScCGMen+Y0ANt/L TpVq7L5lWKjYMt6imT8WZeN0UuGiTDq82isEkRPOtUCWueZ57GZjTGcoo5XbQ9Xg/OHk x6wCZ7ys4RLV4ARc+0Ut8EBZ1k8Zr6pbpEWifgmrYI+3lTYGBclvoJG8eIWC22W2Y8MQ DZRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l9Ts5DM981lqeJ00fftKEbTxkjTHmKPfGAXmwGATixo=; b=Fief/niHrdCA8IRBmjSgqGEoqQs5n5kes9kea60xWnxrGnKIdjsSFDaqKWH0bq9jFZ 3vUKnOIBcwyFVU4oIpPrmURFi3PEtEvTgxMJEbjhZ8iBL0RhLX3B1UaCacflvdE1kva7 hLKUFUs1gOWu8lwtiADYGutisrGw1Xbq4h9RIrbQcciq7/LAFkm6Si8uhrZmNKt/e+CM BWJmXoZWf6Ll80dRUgQtThI47KEcFw3gExh4vrE7nIoIa6RlzbdF+MdNPUMZbBvCwFLH d+JPXQloS3e2+pyBVJ3V4zCxj220NQbhYTF2NJ+JiNUvp5HJfaxW8gLdcJZbHbgEVmyi p1Rw== X-Gm-Message-State: AN3rC/7XRWBRepliTBtI9G41FnFoiUA3Osg+cb1MdFPGjsNmvuYJpf3s fhqqJ9B+r+2A5g== X-Received: by 10.55.43.144 with SMTP id r16mr8489262qkr.213.1493904908778; Thu, 04 May 2017 06:35:08 -0700 (PDT) Received: from localhost (nat-pool-bos-t.redhat.com. [66.187.233.206]) by smtp.gmail.com with ESMTPSA id k34sm1367008qte.3.2017.05.04.06.35.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 04 May 2017 06:35:07 -0700 (PDT) From: Rob Clark To: iommu@lists.linux-foundation.org Cc: linux-arm-msm@vger.kernel.org, Robin Murphy , Will Deacon , Sricharan , Mark Rutland , Stanimir Varbanov , Archit Taneja , Rob Herring , Rob Clark , devicetree@vger.kernel.org Subject: [PATCH 1/4] Docs: dt: document qcom iommu bindings Date: Thu, 4 May 2017 09:34:33 -0400 Message-Id: <20170504133436.24288-2-robdclark@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170504133436.24288-1-robdclark@gmail.com> References: <20170504133436.24288-1-robdclark@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Clark Reviewed-by: Rob Herring --- .../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt new file mode 100644 index 0000000..0d50f84 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -0,0 +1,121 @@ +* QCOM IOMMU v1 Implementation + +Qualcomm "B" family devices which are not compatible with arm-smmu have +a similar looking IOMMU but without access to the global register space, +and optionally requiring additional configuration to route context irqs +to non-secure vs secure interrupt line. + +** Required properties: + +- compatible : Should be one of: + + "qcom,msm8916-iommu" + + Followed by "qcom,msm-iommu-v1". + +- clock-names : Should be a pair of "iface" (required for IOMMUs + register group access) and "bus" (required for + the IOMMUs underlying bus access). + +- clocks : Phandles for respective clocks described by + clock-names. + +- #address-cells : must be 1. + +- #size-cells : must be 1. + +- #iommu-cells : Must be 1. + +- ranges : Base address and size of the iommu context banks. + +- qcom,iommu-secure-id : secure-id. + +- List of sub-nodes, one per translation context bank. Each sub-node + has the following required properties: + + - compatible : Should be one of: + - "qcom,msm-iommu-v1-ns" : non-secure context bank + - "qcom,msm-iommu-v1-sec" : secure context bank + - reg : Base address and size of context bank within the iommu + - interrupts : The context fault irq. + +** Optional properties: + +- reg : Base address and size of the SMMU local base, should + be only specified if the iommu requires configuration + for routing of context bank irq's to secure vs non- + secure lines. (Ie. if the iommu contains secure + context banks) + + +** Examples: + + apps_iommu: iommu@1e20000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1f09000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@1f0a000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + ... + + venus: video-codec@1d00000 { + ... + iommus = <&apps_iommu 5>; + }; + + mdp: mdp@1a01000 { + ... + iommus = <&apps_iommu 4>; + }; + + gpu@01c00000 { + ... + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + };