From patchwork Wed Aug 3 00:30:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 655187 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s3vB2307Pz9sRZ for ; Wed, 3 Aug 2016 10:30:50 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=J9vVEd+Z; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756918AbcHCAas (ORCPT ); Tue, 2 Aug 2016 20:30:48 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:35282 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756914AbcHCAar (ORCPT ); Tue, 2 Aug 2016 20:30:47 -0400 Received: by mail-pa0-f48.google.com with SMTP id iw10so67887521pac.2 for ; Tue, 02 Aug 2016 17:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pTmi2EqPdYaqlunig6N0SZunabrtxINUv1BqpscjseU=; b=J9vVEd+ZPVU/HPPrHfq8H6H1iqhFd6uih6ceGXEd9fA57DHV2fSDvj3gIpv0KuOca0 IrvFHGnpJV2df1c/af7kAXHNkFTz39NhwViRkJoCySGL8I0MC3nP0H4oWdCEUvP0d+uO mSSD6qJP0fS6A+1bxzJ8o6XsPOF/IaNzo0tEkznIxG0bH1vcxTSLkRjbp05s84PwNCRF vPeDBQ5pq+5Wc/qw7XEhhSzS30twK0+EPrxg9rliMvWhZBB2uzM2snnoxFRMUG0nJmFy jIfp0EWMhV3uNVDgylohZedtlOmNqEUAjNcpj2LM6KA6J1ets7/zRWkkRXoFtEh5OqoJ im5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pTmi2EqPdYaqlunig6N0SZunabrtxINUv1BqpscjseU=; b=QoZ3T/5obr1KhAfWHLS8Y6oWS/q3LxO4aCJWTAgJLU+7cswafwLymlFM5PSTvfOSCL 7+8bPH0oqqkmtlGmJmFuuvIfErX9dAc6ewXrL6xqeKTcDS/RzsYepgFQhvauhAciKm3Q ZfXBikenP0vwOWhzE+8qcywXHjlV24rABLRqdWHSVP3sVnCeBCFgPQOHoeuIGsDe4LfS lAdNWJhm3odvIGvZigwuviI6hBcCXbRi6Ahf/MPIh7ARYKFy7YIf88LHN2+pZKZ6n7J9 +4HHb/QRTculOMiCCwSGkuXRIGjAHnmjGbjGvEHrKs5YWu+zdYqDCMcE14fA5viUPKBn BMfw== X-Gm-Message-State: AEkooutknH3tCGy5cc62omtP2OQVA459Wkb2HPFSLMyv2zVsVGL3cMtPOgDrpDh4P2IUrcOp X-Received: by 10.66.49.6 with SMTP id q6mr52670121pan.48.1470184246644; Tue, 02 Aug 2016 17:30:46 -0700 (PDT) Received: from localhost (c-98-203-232-209.hsd1.wa.comcast.net. [98.203.232.209]) by smtp.gmail.com with ESMTPSA id tr1sm7486228pab.19.2016.08.02.17.30.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Aug 2016 17:30:46 -0700 (PDT) From: Kevin Hilman To: Ulf Hansson , linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] ARM64: dts: meson-gxbb: add MMC support Date: Tue, 2 Aug 2016 17:30:44 -0700 Message-Id: <20160803003045.24980-1-khilman@baylibre.com> X-Mailer: git-send-email 2.9.0 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding and basic support for the SD/eMMC controller on Amlogic S905/GXBB devices. Signed-off-by: Kevin Hilman --- .../devicetree/bindings/mmc/amlogic,meson-gxbb.txt | 29 +++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 74 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 71 +++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 30 ++++++++- 4 files changed, 203 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt new file mode 100644 index 000000000000..2bfdf47018c5 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt @@ -0,0 +1,29 @@ +Amlogic SD / eMMC controller for S905/GXBB family SoCs + +The MMC 5.1 compliant host controller on Amlogic provides the +interface for SD, eMMC and SDIO devices. + +This file documents the properties in addition to those available in +the MMC core bindings, documented by mmc.txt. + +Required properties: +- compatible : contains "amlogic,meson-gxbb" +- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names. +- clock-names: Should contain the following: + "core" - Main peripheral bus clock + "clkin0" - Parent clock of internal mux + "clkin1" - Other parent clock of internal mux + The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the + clock rate requested by the MMC core. + +Example: + + sd_emmc_a: mmc@70000 { + compatible = "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x70000 0x0 0x2000>; + interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + pinctrl-0 = <&emmc_pins>; + }; + diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 90a84c514d3d..a49f7f77eb34 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -73,6 +73,45 @@ default-state = "off"; }; }; + + mmc_iv: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "mmc-gpio-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + gpio-states = <0 1>; + + /* + * Based on ODROID-C2 schematics: + * signal name: IO_TF_3V3N_1V8, GPIOAO bit 3 + */ + states = <3300000 0 + 1800000 1>; + }; + + vcc1v8: regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; }; &uart_AO { @@ -87,3 +126,38 @@ pinctrl-names = "default"; }; +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + vmmc-supply = <&mmc_iv>; + voltage-ranges = <1800 3300>; +}; + +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + voltage-ranges = <1800 3300>; + vmmc-supply = <&vcc3v3>; + vmmcq-sumpply = <&vcc1v8>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index f4f30f674b4c..63d95d136aec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -57,6 +57,42 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; + + mmc_iv: gpio-regulator { + compatible = "regulator-gpio"; + + regulator-name = "mmc-gpio-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + gpio-states = <0 1>; + + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */ + states = <1800000 0 + 3300000 1>; + }; + + vddio_boot: regulator { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; }; /* This UART is brought out to the DB9 connector */ @@ -72,3 +108,38 @@ pinctrl-names = "default"; }; +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + cd-inverted; + + voltage-ranges = <1800 3300>; + vmmc-supply = <&mmc_iv>; +}; + +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <200000000>; + non-removable; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + mmc-pwrseq = <&emmc_pwrseq>; + voltage-ranges = <1800 3300>; + vmmc-supply = <&vcc_3v3>; + vmmcq-sumpply = <&vddio_boot>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 35c8b2beb05c..2e48fa1e0364 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -247,7 +247,8 @@ mux { groups = "emmc_nand_d07", "emmc_cmd", - "emmc_clk"; + "emmc_clk", + "emmc_ds"; function = "emmc"; }; }; @@ -330,6 +331,33 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; + + sd_emmc_a: mmc@70000 { + compatible = "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x70000 0x0 0x2000>; + interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; + clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + status = "disabled"; + }; + + sd_emmc_b: mmc@72000 { + compatible = "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x72000 0x0 0x2000>; + interrupts = < GIC_SPI 217 IRQ_TYPE_EDGE_RISING >; + clocks = <&clkc CLKID_SD_EMMC_B>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + status = "disabled"; + }; + + sd_emmc_c: mmc@74000 { + compatible = "amlogic,meson-gxbb-mmc"; + reg = <0x0 0x74000 0x0 0x2000>; + interrupts = < GIC_SPI 218 IRQ_TYPE_EDGE_RISING >; + clocks = <&clkc CLKID_SD_EMMC_C>, <&xtal>, <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + status = "disabled"; + }; }; ethmac: ethernet@c9410000 {