| Message ID | 1730705521-23081-3-git-send-email-shawn.lin@rock-chips.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Initial support for RK3576 UFS controller | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Mon, Nov 04, 2024 at 03:31:56PM +0800, Shawn Lin wrote: > Document Rockchip UFS host controller for RK3576 SoC. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > --- > > Changes in v4: > - properly describe reset-gpios > > Changes in v3: > - rename the file to rockchip,rk3576-ufshc.yaml > - add description for reset-gpios > - use rockchip,rk3576-ufshc as compatible > > Changes in v2: > - rename the file > - add reset-gpios > > .../bindings/ufs/rockchip,rk3576-ufshc.yaml | 105 +++++++++++++++++++++ > 1 file changed, 105 insertions(+) > create mode 100644 Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml > > diff --git a/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml > new file mode 100644 > index 0000000..bc4c3de > --- /dev/null > +++ b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml > @@ -0,0 +1,105 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip UFS Host Controller > + > +maintainers: > + - Shawn Lin <shawn.lin@rock-chips.com> > + > +allOf: > + - $ref: ufs-common.yaml > + > +properties: > + compatible: > + const: rockchip,rk3576-ufshc > + > + reg: > + maxItems: 5 > + > + reg-names: > + items: > + - const: hci > + - const: mphy > + - const: hci_grf > + - const: mphy_grf > + - const: hci_apb > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: core > + - const: pclk > + - const: pclk_mphy > + - const: ref_out > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 4 > + > + reset-names: > + items: > + - const: biu > + - const: sys > + - const: ufs > + - const: grf > + > + reset-gpios: > + maxItems: 1 > + description: | > + GPIO specifiers for host to reset the whole UFS device including PHY and > + memory. This gpio is active low and should choose the one whose high output > + voltage is lower than 1.5V based on the UFS spec. > + > +required: > + - compatible > + - reg > + - reg-names > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - resets > + - reset-names > + - reset-gpios > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rockchip,rk3576-cru.h> > + #include <dt-bindings/reset/rockchip,rk3576-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/rockchip,rk3576-power.h> > + #include <dt-bindings/pinctrl/rockchip.h> > + #include <dt-bindings/gpio/gpio.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + ufs: ufs@2a2d0000 { Could you please use 'ufshc' as the node name as documented in the devicetree spec? - Mani > + compatible = "rockchip,rk3576-ufshc"; > + reg = <0x0 0x2a2d0000 0x0 0x10000>, > + <0x0 0x2b040000 0x0 0x10000>, > + <0x0 0x2601f000 0x0 0x1000>, > + <0x0 0x2603c000 0x0 0x1000>, > + <0x0 0x2a2e0000 0x0 0x10000>; > + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; > + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, > + <&cru CLK_REF_UFS_CLKOUT>; > + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; > + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&power RK3576_PD_USB>; > + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, > + <&cru SRST_P_UFS_GRF>; > + reset-names = "biu", "sys", "ufs", "grf"; > + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; > + }; > + }; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml new file mode 100644 index 0000000..bc4c3de --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip UFS Host Controller + +maintainers: + - Shawn Lin <shawn.lin@rock-chips.com> + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: rockchip,rk3576-ufshc + + reg: + maxItems: 5 + + reg-names: + items: + - const: hci + - const: mphy + - const: hci_grf + - const: mphy_grf + - const: hci_apb + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pclk + - const: pclk_mphy + - const: ref_out + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: biu + - const: sys + - const: ufs + - const: grf + + reset-gpios: + maxItems: 1 + description: | + GPIO specifiers for host to reset the whole UFS device including PHY and + memory. This gpio is active low and should choose the one whose high output + voltage is lower than 1.5V based on the UFS spec. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - power-domains + - resets + - reset-names + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3576-cru.h> + #include <dt-bindings/reset/rockchip,rk3576-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rockchip,rk3576-power.h> + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufs: ufs@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3576_PD_USB>; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, + <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + }; + };