| Message ID | 1713939683-15328-3-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add i.MX8QM HSIO PHY driver | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success | |
| robh/dtbs-check | warning | build log |
| robh/dt-meta-schema | success |
On Wed, Apr 24, 2024 at 02:21:22PM +0800, Richard Zhu wrote: > Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. > Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at > initialization according to board design. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > new file mode 100644 > index 000000000000..3e2824d1616c > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale i.MX8QM SoC series HSIO SERDES PHY > + > +maintainers: > + - Richard Zhu <hongxing.zhu@nxp.com> > + > +properties: > + compatible: > + enum: > + - fsl,imx8qm-hsio > + - fsl,imx8qxp-hsio > + reg: > + minItems: 4 > + maxItems: 4 > + > + "#phy-cells": > + const: 3 > + description: > + The first defines the type of the PHY refer to the include phy.h. > + The second defines controller index. > + The third defines the lane mask of the lane ID, indicated which > + lane is used by the PHY. They are defined as HSIO_LAN* in > + dt-bindings/phy/phy-imx8-pcie.h > + > + reg-names: > + items: > + - const: reg > + - const: phy > + - const: ctrl > + - const: misc > + > + clocks: > + minItems: 5 > + maxItems: 14 > + > + clock-names: > + minItems: 5 > + maxItems: 14 > + > + fsl,hsio-cfg: > + description: Refer macro HSIO_CFG* include/dt-bindings/phy/phy-imx8-pcie.h. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + fsl,refclk-pad-mode: > + description: > + Specifies the mode of the refclk pad used. It can be UNUSED(PHY > + refclock is derived from SoC internal source), INPUT(PHY refclock > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > + is derived from SoC internal source and provided on the refclk pad). > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > + to be used. > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: IMX8_PCIE_REFCLK_PAD_OUTPUT My comments on this are still not addressed. Please go back and read my comments about this property on v1.
On Wed, Apr 24, 2024 at 01:04:27PM +0100, Conor Dooley wrote: > On Wed, Apr 24, 2024 at 02:21:22PM +0800, Richard Zhu wrote: > > Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. > > Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at > > initialization according to board design. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > --- > > .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 ++++++++++++++++++ > > 1 file changed, 146 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > > > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > new file mode 100644 > > index 000000000000..3e2824d1616c > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > @@ -0,0 +1,146 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Freescale i.MX8QM SoC series HSIO SERDES PHY > > + > > +maintainers: > > + - Richard Zhu <hongxing.zhu@nxp.com> > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx8qm-hsio > > + - fsl,imx8qxp-hsio > > + reg: > > + minItems: 4 > > + maxItems: 4 > > + > > + "#phy-cells": > > + const: 3 > > + description: > > + The first defines the type of the PHY refer to the include phy.h. > > + The second defines controller index. > > + The third defines the lane mask of the lane ID, indicated which > > + lane is used by the PHY. They are defined as HSIO_LAN* in > > + dt-bindings/phy/phy-imx8-pcie.h > > + > > + reg-names: > > + items: > > + - const: reg > > + - const: phy > > + - const: ctrl > > + - const: misc > > + > > + clocks: > > + minItems: 5 > > + maxItems: 14 > > + > > + clock-names: > > + minItems: 5 > > + maxItems: 14 > > + > > + fsl,hsio-cfg: > > + description: Refer macro HSIO_CFG* include/dt-bindings/phy/phy-imx8-pcie.h. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + fsl,refclk-pad-mode: > > + description: > > + Specifies the mode of the refclk pad used. It can be UNUSED(PHY > > + refclock is derived from SoC internal source), INPUT(PHY refclock > > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > > + is derived from SoC internal source and provided on the refclk pad). > > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > > + to be used. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + default: IMX8_PCIE_REFCLK_PAD_OUTPUT > > My comments on this are still not addressed. Please go back and read my > comments about this property on v1. Richard: I think we missunderstand conor's means at v1. "Why do we need numbers and a header here at all? The enum should be an enum of strings input, output & unused. Oh and "unused" can just be dropped, and not having the property at all would mean "unused"." fsl,refclk-pad-mode: description: ... enum: ["input", "output"]. If not exist "fsl,refclk-pad-mode" means "unused". Frank
> -----Original Message----- > From: Frank Li <frank.li@nxp.com> > Sent: 2024年4月24日 22:39 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: Hongxing Zhu <hongxing.zhu@nxp.com>; vkoul@kernel.org; > kishon@kernel.org; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > conor+dt@kernel.org; linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; imx@lists.linux.dev > Subject: Re: [PATCH v3 2/3] dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY > binding > > On Wed, Apr 24, 2024 at 01:04:27PM +0100, Conor Dooley wrote: > > On Wed, Apr 24, 2024 at 02:21:22PM +0800, Richard Zhu wrote: > > > Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. > > > Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set > > > at initialization according to board design. > > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > > --- > > > .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 > ++++++++++++++++++ > > > 1 file changed, 146 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > > b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > > new file mode 100644 > > > index 000000000000..3e2824d1616c > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml > > > @@ -0,0 +1,146 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Freescale i.MX8QM SoC series HSIO SERDES PHY > > > + > > > +maintainers: > > > + - Richard Zhu <hongxing.zhu@nxp.com> > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - fsl,imx8qm-hsio > > > + - fsl,imx8qxp-hsio > > > + reg: > > > + minItems: 4 > > > + maxItems: 4 > > > + > > > + "#phy-cells": > > > + const: 3 > > > + description: > > > + The first defines the type of the PHY refer to the include phy.h. > > > + The second defines controller index. > > > + The third defines the lane mask of the lane ID, indicated which > > > + lane is used by the PHY. They are defined as HSIO_LAN* in > > > + dt-bindings/phy/phy-imx8-pcie.h > > > + > > > + reg-names: > > > + items: > > > + - const: reg > > > + - const: phy > > > + - const: ctrl > > > + - const: misc > > > + > > > + clocks: > > > + minItems: 5 > > > + maxItems: 14 > > > + > > > + clock-names: > > > + minItems: 5 > > > + maxItems: 14 > > > + > > > + fsl,hsio-cfg: > > > + description: Refer macro HSIO_CFG* > include/dt-bindings/phy/phy-imx8-pcie.h. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + > > > + fsl,refclk-pad-mode: > > > + description: > > > + Specifies the mode of the refclk pad used. It can be UNUSED(PHY > > > + refclock is derived from SoC internal source), INPUT(PHY refclock > > > + is provided externally via the refclk pad) or OUTPUT(PHY refclock > > > + is derived from SoC internal source and provided on the refclk pad). > > > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants > > > + to be used. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + default: IMX8_PCIE_REFCLK_PAD_OUTPUT > > > > My comments on this are still not addressed. Please go back and read > > my comments about this property on v1. Hi Conor: Thanks for your comments. As Frank said below, your comments are misunderstand. > > Richard: I think we missunderstand conor's means at v1. > > "Why do we need numbers and a header here at all? The enum should be an > enum of strings input, output & unused. Oh and "unused" can just be dropped, > and not having the property at all would mean "unused"." > > fsl,refclk-pad-mode: > description: > ... > enum: ["input", "output"]. > > If not exist "fsl,refclk-pad-mode" means "unused". > > Frank Thanks. Would be changed as this way later. Best Regards Richard Zhu
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml new file mode 100644 index 000000000000..3e2824d1616c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8QM SoC series HSIO SERDES PHY + +maintainers: + - Richard Zhu <hongxing.zhu@nxp.com> + +properties: + compatible: + enum: + - fsl,imx8qm-hsio + - fsl,imx8qxp-hsio + reg: + minItems: 4 + maxItems: 4 + + "#phy-cells": + const: 3 + description: + The first defines the type of the PHY refer to the include phy.h. + The second defines controller index. + The third defines the lane mask of the lane ID, indicated which + lane is used by the PHY. They are defined as HSIO_LAN* in + dt-bindings/phy/phy-imx8-pcie.h + + reg-names: + items: + - const: reg + - const: phy + - const: ctrl + - const: misc + + clocks: + minItems: 5 + maxItems: 14 + + clock-names: + minItems: 5 + maxItems: 14 + + fsl,hsio-cfg: + description: Refer macro HSIO_CFG* include/dt-bindings/phy/phy-imx8-pcie.h. + $ref: /schemas/types.yaml#/definitions/uint32 + + fsl,refclk-pad-mode: + description: + Specifies the mode of the refclk pad used. It can be UNUSED(PHY + refclock is derived from SoC internal source), INPUT(PHY refclock + is provided externally via the refclk pad) or OUTPUT(PHY refclock + is derived from SoC internal source and provided on the refclk pad). + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants + to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + default: IMX8_PCIE_REFCLK_PAD_OUTPUT + + power-domains: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - clocks + - clock-names + - fsl,hsio-cfg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qxp-hsio + then: + properties: + clock-names: + items: + - const: pclk0 + - const: apb_pclk0 + - const: phy0_crr + - const: ctl0_crr + - const: misc_crr + power-domains: + minItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-hsio + then: + properties: + clock-names: + items: + - const: pclk0 + - const: pclk1 + - const: apb_pclk0 + - const: apb_pclk1 + - const: pclk2 + - const: epcs_tx + - const: epcs_rx + - const: apb_pclk2 + - const: phy0_crr + - const: phy1_crr + - const: ctl0_crr + - const: ctl1_crr + - const: ctl2_crr + - const: misc_crr + power-domains: + minItems: 2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx8-clock.h> + #include <dt-bindings/clock/imx8-lpcg.h> + #include <dt-bindings/firmware/imx/rsrc.h> + #include <dt-bindings/phy/phy-imx8-pcie.h> + + phy@5f1a0000 { + compatible = "fsl,imx8qxp-hsio"; + reg = <0x5f1a0000 0x10000>, + <0x5f120000 0x10000>, + <0x5f140000 0x10000>, + <0x5f160000 0x10000>; + reg-names = "reg", "phy", "ctrl", "misc"; + clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>, + <&phyx1_lpcg IMX_LPCG_CLK_4>, + <&phyx1_crr1_lpcg IMX_LPCG_CLK_4>, + <&pcieb_crr3_lpcg IMX_LPCG_CLK_4>, + <&misc_crr5_lpcg IMX_LPCG_CLK_4>; + clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr", "misc_crr"; + power-domains = <&pd IMX_SC_R_SERDES_1>; + #phy-cells = <3>; + fsl,hsio-cfg = <IMX8Q_HSIO_CFG_PCIEB>; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + }; +...
Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding. Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at initialization according to board design. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- .../bindings/phy/fsl,imx8qm-hsio.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8qm-hsio.yaml