| Message ID | 1711699790-16494-3-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add i.MX8Q HSIO PHY driver support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/patch-applied | success |
On Fri, Mar 29, 2024 at 04:09:49PM +0800, Richard Zhu wrote: > Add binding for controller ID and HSIO configuration setting of the > i.MX8Q HSIO SerDes PHY. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > include/dt-bindings/phy/phy-imx8-pcie.h | 26 +++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) This one should be first patch. (1/3). After fix small improve Reviewed-by: Frank Li <Frank.Li@nxp.com> > > diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h > index 8bbe2d6538d8..5cd5580879fa 100644 > --- a/include/dt-bindings/phy/phy-imx8-pcie.h > +++ b/include/dt-bindings/phy/phy-imx8-pcie.h > @@ -11,4 +11,30 @@ > #define IMX8_PCIE_REFCLK_PAD_INPUT 1 > #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 > > +/* > + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: > + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one > + * lane) and SATA. Suggest add empty line between segment. > + * In the different use cases. PCIEA can be binded to PHY lane0, lane1 > + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA > + * can only be binded to last lane2 PHY. > + * Define i.MX8Q HSIO controller ID here to specify the controller > + * binded to the PHY. > + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only > + * support one lane) controller. > + */ > +#define IMX8Q_HSIO_PCIEA_ID 0 > +#define IMX8Q_HSIO_PCIEB_ID 1 > +#define IMX8Q_HSIO_SATA_ID 2 > + > +/* > + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. > + * Define configurations beside PCIEA is enabled. > + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. > + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. > + */ > +#define IMX8Q_HSIO_CFG_SATA 1 > +#define IMX8Q_HSIO_CFG_PCIEB 2 > +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 > + > #endif /* _DT_BINDINGS_IMX8_PCIE_H */ > -- > 2.37.1 >
> -----Original Message----- > From: Frank Li <frank.li@nxp.com> > Sent: 2024年3月29日 22:21 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: vkoul@kernel.org; kishon@kernel.org; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org; > linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH v1 2/3] dt-bindings: phy: phy-imx8-pcie: Add binding for > i.MX8Q HSIO SerDes PHY > > On Fri, Mar 29, 2024 at 04:09:49PM +0800, Richard Zhu wrote: > > Add binding for controller ID and HSIO configuration setting of the > > i.MX8Q HSIO SerDes PHY. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > --- > > include/dt-bindings/phy/phy-imx8-pcie.h | 26 > > +++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > This one should be first patch. (1/3). > > After fix small improve > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > Thanks for your review. > > > > diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h > > b/include/dt-bindings/phy/phy-imx8-pcie.h > > index 8bbe2d6538d8..5cd5580879fa 100644 > > --- a/include/dt-bindings/phy/phy-imx8-pcie.h > > +++ b/include/dt-bindings/phy/phy-imx8-pcie.h > > @@ -11,4 +11,30 @@ > > #define IMX8_PCIE_REFCLK_PAD_INPUT 1 > > #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 > > > > +/* > > + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: > > + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one > > + * lane) and SATA. > > Suggest add empty line between segment. > Okay, would be added later. Thanks. Best Regards Richard Zhu > > + * In the different use cases. PCIEA can be binded to PHY lane0, > > +lane1 > > + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. > > +SATA > > + * can only be binded to last lane2 PHY. > > + * Define i.MX8Q HSIO controller ID here to specify the controller > > + * binded to the PHY. > > + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only > > + * support one lane) controller. > > + */ > > +#define IMX8Q_HSIO_PCIEA_ID 0 > > +#define IMX8Q_HSIO_PCIEB_ID 1 > > +#define IMX8Q_HSIO_SATA_ID 2 > > + > > +/* > > + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. > > + * Define configurations beside PCIEA is enabled. > > + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. > > + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. > > + */ > > +#define IMX8Q_HSIO_CFG_SATA 1 > > +#define IMX8Q_HSIO_CFG_PCIEB 2 > > +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 > > + > > #endif /* _DT_BINDINGS_IMX8_PCIE_H */ > > -- > > 2.37.1 > >
diff --git a/include/dt-bindings/phy/phy-imx8-pcie.h b/include/dt-bindings/phy/phy-imx8-pcie.h index 8bbe2d6538d8..5cd5580879fa 100644 --- a/include/dt-bindings/phy/phy-imx8-pcie.h +++ b/include/dt-bindings/phy/phy-imx8-pcie.h @@ -11,4 +11,30 @@ #define IMX8_PCIE_REFCLK_PAD_INPUT 1 #define IMX8_PCIE_REFCLK_PAD_OUTPUT 2 +/* + * i.MX8QM HSIO subsystem has three lane PHYs and three controllers: + * PCIEA(2 lanes capapble PCIe controller), PCIEB (only support one + * lane) and SATA. + * In the different use cases. PCIEA can be binded to PHY lane0, lane1 + * or Lane0 and lane1. PCIEB can be binded to lane1 or lane2 PHY. SATA + * can only be binded to last lane2 PHY. + * Define i.MX8Q HSIO controller ID here to specify the controller + * binded to the PHY. + * Meanwhile, i.MX8QXP HSIO subsystem has one lane PHY and PCIEB(only + * support one lane) controller. + */ +#define IMX8Q_HSIO_PCIEA_ID 0 +#define IMX8Q_HSIO_PCIEB_ID 1 +#define IMX8Q_HSIO_SATA_ID 2 + +/* + * On i.MX8QM, PCIEA is mandatory required if the HSIO is enabled. + * Define configurations beside PCIEA is enabled. + * On i.MX8QXP, HSIO module only has PCIEB and one lane PHY. + * The "IMX8Q_HSIO_CFG_PCIEB" can be used on i.MX8QXP platforms. + */ +#define IMX8Q_HSIO_CFG_SATA 1 +#define IMX8Q_HSIO_CFG_PCIEB 2 +#define IMX8Q_HSIO_CFG_PCIEBSATA 3 + #endif /* _DT_BINDINGS_IMX8_PCIE_H */
Add binding for controller ID and HSIO configuration setting of the i.MX8Q HSIO SerDes PHY. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- include/dt-bindings/phy/phy-imx8-pcie.h | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+)