From patchwork Tue Nov 3 07:59:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmlheGluIFl1ICjkv57lrrbpkasp?= X-Patchwork-Id: 1392703 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=XHjZTwak; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CQMdQ6hpxz9sRR for ; Tue, 3 Nov 2020 18:59:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726938AbgKCH7y (ORCPT ); Tue, 3 Nov 2020 02:59:54 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:53677 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725982AbgKCH7y (ORCPT ); Tue, 3 Nov 2020 02:59:54 -0500 X-UUID: b49463b3748547fb9ab577f9d8370c87-20201103 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=3AjCwyELXJsAF7KDdOI9+UHESz6oEunbkSh/sKmq2DQ=; b=XHjZTwakj15FEalg7d7rD3uLi0JUIxFv/WdWqmjKj1Ef4mxFoJJrrt0Axuq2OvQtf/AVeglMFAbCd2dcXKPbSxAGw3CKgwKVccrGh8i9PmV3gIr/ltKDCr2bjdkyAGl+7/SKeAgNKwuV9UBj3gSHs4+YEtkSs4lgkuB+QyGMPgo=; X-UUID: b49463b3748547fb9ab577f9d8370c87-20201103 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1619352867; Tue, 03 Nov 2020 15:59:50 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 3 Nov 2020 15:59:49 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 3 Nov 2020 15:59:48 +0800 From: Jiaxin Yu To: , , , , , , , , , CC: , , , , Jiaxin Yu Subject: [PATCH v4 7/9] dt-bindings: mediatek: mt8192: add audio afe document Date: Tue, 3 Nov 2020 15:59:36 +0800 Message-ID: <1604390378-23993-8-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1604390378-23993-1-git-send-email-jiaxin.yu@mediatek.com> References: <1604390378-23993-1-git-send-email-jiaxin.yu@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds mt8192 audio afe document. Signed-off-by: Jiaxin Yu --- This patch depends on following series that has not been accepted: https://patchwork.kernel.org/cover/11752231 (dt-bindings/clock/mt8192-clk.h is included in it.) https://patchwork.kernel.org/patch/11755895 (dt-bindings/power/mt8192-power.h is included in it.) https://lore.kernel.org/patchwork/patch/1321118 (dt-bindings/reset-controller/mt8192-resets.h is included in it.) .../bindings/sound/mt8192-afe-pcm.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml new file mode 100644 index 0000000000000..0170c93802d29 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek AFE PCM controller for mt8192 + +maintainers: + - Jiaxin Yu + - Shane Chien + +properties: + compatible: + const: mediatek,mt8192-audio + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + mediatek,apmixedsys: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek apmixedsys controller + + mediatek,infracfg: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek infracfg controller + + mediatek,topckgen: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: The phandle of the mediatek topckgen controller + + power-domains: + maxItems: 1 + + clocks: + items: + - description: AFE clock + - description: ADDA DAC clock + - description: ADDA DAC pre-distortion clock + - description: audio infra sys clock + - description: audio infra 26M clock + + clock-names: + items: + - const: aud_afe_clk + - const: aud_dac_clk + - const: aud_dac_predis_clk + - const: aud_infra_clk + - const: aud_infra_26m_clk + +required: + - compatible + - interrupts + - resets + - reset-names + - mediatek,apmixedsys + - mediatek,infracfg + - mediatek,topckgen + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = ; + resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg>; + mediatek,topckgen = <&topckgen>; + power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_infra_clk", + "aud_infra_26m_clk"; + }; + +...