[1/3] dt-bindings: mmc: fsl-imx-esdhc: add imx6ull compatible string

Add imx6ull compatible string

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 1 +
 1 file changed, 1 insertion(+)

On 20/12/18 9:49 AM, BOUGH CHEN wrote:
> i.MX6ULL has errata ERR010450, point out that due to SOC I/O
> timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the
> clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO
> DDR50 mode, the clock rate can't exceed 45MHz.
> 
> This patch add this limit for imx6ull.
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Apart from the kbuild test robot complaints (do they need to be fixed?):

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index d0d3193..75a2484 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -138,7 +138,11 @@
>  #define ESDHC_FLAG_HS200		BIT(8)
>  /* The IP supports HS400 mode */
>  #define ESDHC_FLAG_HS400		BIT(9)
> -
> +/* The IP has errata ERR010450
> + * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't
> + * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
> + */
> +#define ESDHC_FLAG_ERR010450           BIT(10)
>  /* A clock frequency higher than this rate requires strobe dll control */
>  #define ESDHC_STROBE_DLL_CLK_FREQ	100000000
>  
> @@ -177,6 +181,12 @@ struct esdhc_soc_data {
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
>  };
>  
> +static struct esdhc_soc_data usdhc_imx6ull_data = {
> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +			| ESDHC_FLAG_ERR010450,
> +};
> +
>  static struct esdhc_soc_data usdhc_imx7d_data = {
>  	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> @@ -227,6 +237,7 @@ struct pltfm_imx_data {
>  	{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
>  	{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
>  	{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
> +	{ .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
>  	{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
>  	{ /* sentinel */ }
>  };
> @@ -733,6 +744,12 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
>  		| ESDHC_CLOCK_MASK);
>  	sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
>  
> +	if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
> +		if (imx_data->is_ddr)
> +			clock = clock > 45000000 ? 45000000 : clock;
> +		else
> +			clock = clock > 150000000 ? 150000000 : clock;
> +
>  	while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
>  			pre_div < 256)
>  		pre_div *= 2;
>

On Thu, Dec 27, 2018 at 10:01:24AM +0200, Adrian Hunter wrote:
> On 20/12/18 9:49 AM, BOUGH CHEN wrote:
> > i.MX6ULL has errata ERR010450, point out that due to SOC I/O
> > timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the
> > clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO
> > DDR50 mode, the clock rate can't exceed 45MHz.
> > 
> > This patch add this limit for imx6ull.
> > 
> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> 
> Apart from the kbuild test robot complaints (do they need to be fixed?):
> 
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>

Nacked-by: Russell King <rmk+kernel@armlinux.org.uk>

The kbuild test robot complaints do need to be fixed first.  They're
confusing because GCC produces quite a lot of garbage in its error
messages now.  If you look at the patch, there's a hunk that has:

+       if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
+               if (imx_data->is_ddr)
+                       clock = clock > 45000000 ? 45000000 : clock;
+               else
+                       clock = clock > 150000000 ? 150000000 : clock;
+

which is missing a closing brace.  This patch could not have been
build tested before it was mailed to the list, and the test robot
is highlighting that fact.

It may also be a good idea to encourage a different approach to the
above anyway:

	if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
		unsigned long max_clock;

		max_clock = imx_data->is_ddr ? 45000000 : 150000000;

		clock = max(clock, max_clock);
	}

rather than open-coding the max() stuff in the driver.

Thanks.

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
> Sent: 2018年12月27日 20:23
> To: Adrian Hunter <adrian.hunter@intel.com>
> Cc: BOUGH CHEN <haibo.chen@nxp.com>; ulf.hansson@linaro.org;
> robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; Fabio Estevam
> <fabio.estevam@nxp.com>; devicetree@vger.kernel.org;
> linux-mmc@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 2/3] mmc: sdhci-esdhc-imx: add SD clock limitation for
> imx6ull
> 
> On Thu, Dec 27, 2018 at 10:01:24AM +0200, Adrian Hunter wrote:
> > On 20/12/18 9:49 AM, BOUGH CHEN wrote:
> > > i.MX6ULL has errata ERR010450, point out that due to SOC I/O timing
> > > limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the clock rate
> > > can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO
> > > DDR50 mode, the clock rate can't exceed 45MHz.
> > >
> > > This patch add this limit for imx6ull.
> > >
> > > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> >
> > Apart from the kbuild test robot complaints (do they need to be fixed?):
> >
> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> 
> Nacked-by: Russell King <rmk+kernel@armlinux.org.uk>
> 
> The kbuild test robot complaints do need to be fixed first.  They're confusing
> because GCC produces quite a lot of garbage in its error messages now.  If
> you look at the patch, there's a hunk that has:
> 
> +       if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
> +               if (imx_data->is_ddr)
> +                       clock = clock > 45000000 ? 45000000 : clock;
> +               else
> +                       clock = clock > 150000000 ? 150000000 : clock;
> +
> 
> which is missing a closing brace.  This patch could not have been build tested
> before it was mailed to the list, and the test robot is highlighting that fact.
> 

I'm really sorry about that.  Thanks for point out that, I will double check my patch when I mail to the list next time.

> It may also be a good idea to encourage a different approach to the above
> anyway:
> 
> 	if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
> 		unsigned long max_clock;
> 
> 		max_clock = imx_data->is_ddr ? 45000000 : 150000000;
> 
> 		clock = max(clock, max_clock);
> 	}
> 
> rather than open-coding the max() stuff in the driver.

Thanks for giving such a good suggestion, I will take care of it, with a little change:
		clock = min(clock, max_clock);

Best Regard
Bough Chen
> 
> Thanks.
> 
> --
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