| Message ID | 1531718634-17939-4-git-send-email-shubhrajyoti.datta@gmail.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | None | expand |
On Mon, Jul 16, 2018 at 10:53:54AM +0530, shubhrajyoti.datta@gmail.com wrote: > From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > Add binding doc for uartlite A note that this binding is already in use and was undocumented would be nice. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v2: > lowercase for hex values > interrupt description updated > v3: > squashed the clock changes > > .../bindings/serial/xlnx,opb-uartlite.txt | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > create mode 100644 Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > > diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > new file mode 100644 > index 0000000..52719b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > @@ -0,0 +1,23 @@ > +Xilinx Axi Uartlite controller Device Tree Bindings > +--------------------------------------------------------- > + > +Required properties: > +- compatible : Can be either of > + "xlnx,xps-uartlite-1.00.a" > + "xlnx,opb-uartlite-1.00.b" > +- reg : Physical base address and size of the Axi Uartlite > + registers map. > +- interrupts : Should contain UART controller interrupts. How many? > + > +Optional properties: > +- port-number : Set Uart port number > +- clock-names : Should be "s_axi_aclk" > +- clocks : Input clock specifier. Refer to common clock bindings. How do you calc baud rates if this is omitted? > + > +Example: > +serial@800c0000 { > + compatible = "xlnx,xps-uartlite-1.00.a"; > + reg = <0x0 0x800c0000 0x10000>; > + interrupts = <0x0 0x6e 0x1>; > + port-number = <0>; > +}; > -- > 2.7.4 > > -- > To unsubscribe from this list: send the line "unsubscribe devicetree" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
HI Rob, Thanks for the review. > -----Original Message----- > From: Rob Herring [mailto:robh@kernel.org] > Sent: Monday, July 16, 2018 9:33 PM > To: shubhrajyoti.datta@gmail.com > Cc: linux-serial@vger.kernel.org; devicetree@vger.kernel.org; > gregkh@linuxfoundation.org; jacmet@sunsite.dk; Shubhrajyoti Datta > <shubhraj@xilinx.com> > Subject: Re: [PATCHv3 4/4] dt-bindings: serial: Add binding for uartlite > > On Mon, Jul 16, 2018 at 10:53:54AM +0530, shubhrajyoti.datta@gmail.com > wrote: > > From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > > > Add binding doc for uartlite > > A note that this binding is already in use and was undocumented would be > nice. Done in next version. > > > > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > > --- > > v2: > > lowercase for hex values > > interrupt description updated > > v3: > > squashed the clock changes > > > > .../bindings/serial/xlnx,opb-uartlite.txt | 23 ++++++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > > > > diff --git > > a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > > b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > > new file mode 100644 > > index 0000000..52719b9 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt > > @@ -0,0 +1,23 @@ > > +Xilinx Axi Uartlite controller Device Tree Bindings > > +--------------------------------------------------------- > > + > > +Required properties: > > +- compatible : Can be either of > > + "xlnx,xps-uartlite-1.00.a" > > + "xlnx,opb-uartlite-1.00.b" > > +- reg : Physical base address and size of the Axi Uartlite > > + registers map. > > +- interrupts : Should contain UART controller interrupts. > > How many? There is just one interrupt.Fixed in next version. > > > + > > +Optional properties: > > +- port-number : Set Uart port number > > +- clock-names : Should be "s_axi_aclk" > > +- clocks : Input clock specifier. Refer to common clock > bindings. > > How do you calc baud rates if this is omitted? This is a PL (programmable logic ) ip the baud cannot be changed runtime it is decided at design. > > > + > > +Example: > > +serial@800c0000 { > > + compatible = "xlnx,xps-uartlite-1.00.a"; > > + reg = <0x0 0x800c0000 0x10000>; > > + interrupts = <0x0 0x6e 0x1>; > > + port-number = <0>; > > +}; > > -- > > 2.7.4 > > > > -- > > To unsubscribe from this list: send the line "unsubscribe devicetree" > > in the body of a message to majordomo@vger.kernel.org More majordomo > > info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 2018-07-16 18:02, Rob Herring wrote: >> +Optional properties: >> +- port-number : Set Uart port number >> +- clock-names : Should be "s_axi_aclk" >> +- clocks : Input clock specifier. Refer to common clock bindings. > > How do you calc baud rates if this is omitted? The uartlite is fixed to some baud rate (actually divisor) in the fpga. And btw. so are the number of data bits, stop bits and parity. Maarten -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt new file mode 100644 index 0000000..52719b9 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt @@ -0,0 +1,23 @@ +Xilinx Axi Uartlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be either of + "xlnx,xps-uartlite-1.00.a" + "xlnx,opb-uartlite-1.00.b" +- reg : Physical base address and size of the Axi Uartlite + registers map. +- interrupts : Should contain UART controller interrupts. + +Optional properties: +- port-number : Set Uart port number +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. + +Example: +serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x0 0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; +};