From patchwork Mon Jan 8 02:17:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856655 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="Hskahc9D"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFK4s07Mtz9s9Y for ; Mon, 8 Jan 2018 13:30:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754917AbeAHCSZ (ORCPT ); Sun, 7 Jan 2018 21:18:25 -0500 Received: from vern.gendns.com ([206.190.152.46]:50899 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754940AbeAHCSW (ORCPT ); Sun, 7 Jan 2018 21:18:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=mD3NAKH1wbYoqATF8hYwZG7pwcr0dvx5Y5spdi1FOYE=; b=Hskahc9DNMWF4lJFmorJM5gaw IRwhRwE436Zt3kwgLwqA3O9bVSudAuuvn1kFw0vhX79ApuRXl4DRUaFAwVe74pLPacu68uKjMqixF oAD6rMO00daFgFiajy7BPK7Oi5WDkTGVaa+dQmtybyrV0x8tlJzoYTSkJ82V6cOzSin4IcVGB+9ii aMWG9oogLW8F0PJErba6VhAHgsYgnJ0yAfRDxi/pyhFNxOhsPyOAxHZGRDEc4LTADNbbjLH+YsOue zF03Z8Lcc/a7EHUDVC2QKYTjAD/kl6XjQRYXtfscxkMbN706K1vb/PxGjQ1hwN3r67LgP9KxtUKDj 7Ce/rkSHA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN0t-0009GR-Ry; Sun, 07 Jan 2018 21:18:12 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 01/44] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks Date: Sun, 7 Jan 2018 20:17:00 -0600 Message-Id: <1515377863-20358-2-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for the PLL IP blocks in the mach-davinci family of processors. Currently, only the SYSCLKn and AUXCLK outputs are needed, but in the future additional child nodes could be added for OBSCLK and BPDIV. Note: Although these PLL controllers are very similar to the TI Keystone SoCs, we are not re-using those bindings. The Keystone bindings use a legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs have a slightly different PLL register layout and a number of quirks that can't be handled by the existing bindings, so the keystone bindings could not be used as-is anyway. Signed-off-by: David Lechner --- .../devicetree/bindings/clock/ti/davinci/pll.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt new file mode 100644 index 0000000..99bf5da --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt @@ -0,0 +1,47 @@ +Binding for TI DaVinci PLL Controllers + +The PLL provides clocks to most of the components on the SoC. In addition +to the PLL itself, this controller also contains bypasses, gates, dividers, +an multiplexers for various clock signals. + +Required properties: +- compatible: shall be one of: + - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX + - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX +- reg: physical base address and size of the controller's register area. +- clocks: phandle to the PLL input clock source + +Optional child nodes: + +sysclk + Describes the PLLDIVn divider clocks that provide the SYSCLKn clock + domains. The node name must be "sysclk". Consumers of this node should + use "n" in "SYSCLKn" as the parameter for the clock cell. + + Required properties: + - #clock-cells: must be 1 + +auxclk + Describes the AUXCLK output of the PLL. The node name must be "auxclk". + + Required properties: + - #clock-cells: must be 0 + +Examples: + + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>; + + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + + pll0_aux_clk: auxclk { + #clock-cells = <0>; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt