From patchwork Mon Jan 8 02:17:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="OfL/c7g2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFJt92gJQz9s7h for ; Mon, 8 Jan 2018 13:21:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755172AbeAHCS4 (ORCPT ); Sun, 7 Jan 2018 21:18:56 -0500 Received: from vern.gendns.com ([206.190.152.46]:51043 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754923AbeAHCSu (ORCPT ); Sun, 7 Jan 2018 21:18:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=10ZKAtq9+5Hx42gcGz7ZxqSF7c4ltrffaLItmgY+U54=; b=OfL/c7g24sVSUzTnsOQ+B2KoK PHZiQzqPRpAHxVMEOVvpjl5qDx50IJYbwa3jW1655iQFldBema9dYaZx1jYN6cSqh55yCxSf/qWUt MxsShuxRn4lhg+xR4Of7XsNit56GKcRlHUpx7sIvHhUSuJJfD0wbFhcu1sq+LZ9s3p4pMQga443Uf haZ40VbAF8X3FdzECM0uNT8IUr5qKtgPkIcIJjIsb9m+KgKhTZWdckh1US3WMuyj8ShUZSwTgWSUT eskRKuJ9OvV2UWH1pavXOYJmVwjtDDmNV2Dz+4Ce+CX7317oduOG2xBkunRilY5M38cCHVqZM0X7B RTMwLbHug==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN1L-0009GR-DH; Sun, 07 Jan 2018 21:18:39 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 18/44] dt-bindings: clock: Add binding for TI DA8XX CFGCHIP mux clocks Date: Sun, 7 Jan 2018 20:17:17 -0600 Message-Id: <1515377863-20358-19-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for multiplexer clocks that are part of the CFGCHIPn registers on TI DA8XX-like SoCs. Currently, there are only bindings given for the ASYNC3 clock domain, but there are additional clock multiplexers in this syscon that could be added in the future if needed. Signed-off-by: David Lechner --- .../clock/ti/davinci/da8xx-cfgchip-mux.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt new file mode 100644 index 0000000..8c874ad --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt @@ -0,0 +1,42 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP multiplexer clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as clock +multiplexers. This document describes the bindings for those clocks. + +Required properties: +- compatible: shall be "ti,da850-async3-clock". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle list of clocks corresponding to clock-names +- clock-names: must include the following: "pll0_sysclk2", "pll1_sysclk2". + +Optional properties: +- clock-output-names: from common clock binding. + +Parent: +This node must be a child of a "ti,da830-cfgchip" node. + +Assignment: +The assigned-clocks and assigned-clock-parents from the common clock bindings +can be used to indicate which parent clock should be used. + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + async3_clk: async3 { + compatible = "ti,da850-async3-clock"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; + clock-output-names = "async3"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt +