From patchwork Mon Jan 8 02:17:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856653 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="JnB0xRBl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFJw00JHhz9s7h for ; Mon, 8 Jan 2018 13:22:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754951AbeAHCWL (ORCPT ); Sun, 7 Jan 2018 21:22:11 -0500 Received: from vern.gendns.com ([206.190.152.46]:51034 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755136AbeAHCSr (ORCPT ); Sun, 7 Jan 2018 21:18:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=LLxHbzGidSottYKICT6WdNQxTHA0N7gpEwFZ4yIaRqM=; b=JnB0xRBlI2kTXrLaWKZoxQwTp Et00qB/WlG7/rwMdzYzh/oZxVe9MnInue0VJSEc2ksdL0Dz/Qv9ag1b8zbg0Yc0JMCiXExlqNHwsV b2KnSL/w3tt1HadIzerNYbgK/PsaHX3NoCpIyiwZNr776jDmzdJ7C65JwvVZ2027k5S+zd4TBZwux 1zLoNJUcLnT0BXMikC2g2kfGvcVnBxtDE+j4iq6p1Q9Hrur6XT0AvyB8BK3IjU+vFQsYcXT2qxQK9 u8stP0huOqFvfmmtF1H3dp9oSqluPkg08jIv8a6vNeD+P8CP3XHkZQrY12N0QTZzQWwq0DRDKWbuT hn+vJBdmw==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN1J-0009GR-Tw; Sun, 07 Jan 2018 21:18:38 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 17/44] dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks Date: Sun, 7 Jan 2018 20:17:16 -0600 Message-Id: <1515377863-20358-18-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for the gate clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. There are actually other gate clocks in this block that could be added in the future, but TBCLK is currently the only one being used. Signed-off-by: David Lechner --- .../clock/ti/davinci/da8xx-cfgchip-gate.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt new file mode 100644 index 0000000..55821b0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt @@ -0,0 +1,38 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP gate clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as clock +gates. This document describes the bindings for those clocks. + +Required properties: +- compatible: shall be "ti,da830-tbclk". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle to the parent clock + +Optional properties: +- clock-output-names: from common clock binding. + +Parent: +This node must be a child of a "ti,da830-cfgchip" node. + +Assignment: +The assigned-clocks and assigned-clock-parents from the common clock bindings +can be used to indicate which parent clock should be used. + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + ehrpwm_tbclk: tbclk { + compatible = "ti,da830-tbclk"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-output-names = "ehrpwm_tbclk"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt +