From patchwork Wed Dec 20 08:30:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 851323 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=prevas.dk header.i=@prevas.dk header.b="LycpY8FW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3z1nz80JZ3z9s1h for ; Wed, 20 Dec 2017 19:30:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753760AbdLTIam (ORCPT ); Wed, 20 Dec 2017 03:30:42 -0500 Received: from mail02.prevas.se ([62.95.78.10]:10031 "EHLO mail02.prevas.se" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753338AbdLTIal (ORCPT ); Wed, 20 Dec 2017 03:30:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=prevas.dk; i=@prevas.dk; l=2038; q=dns/txt; s=ironport2; t=1513758641; x=1545294641; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=RbXut/ryM1y0w3kT8vwI4qxG4nJLqWfPO9h7yz9MRaE=; b=LycpY8FWQKE/nAsSD4lOtVVEancZZsEJ1Zc37rvEteYBITvHzkaO7qFO mI5/RLAVyITsQs2nf6RroaSSedqqyiiMAUAHKDcMv5ovtogWmgG6qlQUy zeBr/bahZAipOqOBQmHrosHWiJpUXo8U/kLaBwI6jTrQqmBBEg7OseKhm o=; X-IronPort-AV: E=Sophos;i="5.45,431,1508796000"; d="scan'208";a="2832873" Received: from vmprevas3.prevas.se (HELO smtp.prevas.se) ([172.16.8.103]) by ironport2.prevas.se with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2017 09:30:38 +0100 Received: from prevas-ravi.prevas.se (172.16.8.31) by smtp.prevas.se (172.16.8.103) with Microsoft SMTP Server (TLS) id 14.3.361.1; Wed, 20 Dec 2017 09:30:37 +0100 From: Rasmus Villemoes To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Mark Rutland CC: Andy Tang , Shawn Guo , Alexander Stein , Rasmus Villemoes , , Subject: [PATCH v2 2/2] dt/bindings: Add bindings for Layerscape external irqs Date: Wed, 20 Dec 2017 09:30:30 +0100 Message-ID: <1513758631-19909-2-git-send-email-rasmus.villemoes@prevas.dk> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513758631-19909-1-git-send-email-rasmus.villemoes@prevas.dk> References: <1512743580-15358-1-git-send-email-rasmus.villemoes@prevas.dk> <1513758631-19909-1-git-send-email-rasmus.villemoes@prevas.dk> MIME-Version: 1.0 X-Originating-IP: [172.16.8.31] Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Rasmus Villemoes --- .../interrupt-controller/fsl,ls-extirq.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt new file mode 100644 index 000000000000..7e4680866364 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -0,0 +1,37 @@ +* Freescale Layerscape external IRQs + +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting +the polarity of certain external interrupt lines. + +Required properties: +- compatible: should be "fsl,-extirq", e.g. "fsl,ls1021a-extirq". +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: Use the same format as specified by GIC in arm,gic.txt. +- interrupt-parent: phandle of GIC. +- syscon: phandle of Supplemental Configuration Unit (scfg) and offset + to the INTPCR register. +- interrupts: Specifies the mapping to interrupt numbers in the parent + interrupt controller. Interrupts are mapped one-to-one to parent + interrupts. + +Optional properties: +- bit-reverse: This boolean property should be set on the LS1021A if + the SCFGREVCR register has been set to all-ones (which is usually + the case), meaning that all reads and writes of SCFG registers are + implicitly bit-reversed. Other compatible platforms do not have such + a register. + +Example: + extirq: extirq { + compatible = "fsl,ls1021a-extirq"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + syscon = <&scfg 0x1ac>; + interrupts = <163 164 165 167 168 169>; + bit-reverse; + }; + + + interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <&extirq GIC_SPI 1 IRQ_TYPE_LEVEL_LOW>;