From patchwork Fri Jul 7 19:03:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 785721 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3x43sp2txgz9rxm for ; Sat, 8 Jul 2017 05:03:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751892AbdGGTDZ (ORCPT ); Fri, 7 Jul 2017 15:03:25 -0400 Received: from mail.kernel.org ([198.145.29.99]:46382 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750848AbdGGTDY (ORCPT ); Fri, 7 Jul 2017 15:03:24 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 3493922BDF; Fri, 7 Jul 2017 19:03:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3493922BDF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dinguyen@kernel.org From: Dinh Nguyen To: robh+dt@kernel.org Cc: dinguyen@kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCHv1 2/4] ARM: dts: socfpga: add a bypass-reg binding for Stratix10 Date: Fri, 7 Jul 2017 14:03:17 -0500 Message-Id: <1499454199-31901-2-git-send-email-dinguyen@kernel.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499454199-31901-1-git-send-email-dinguyen@kernel.org> References: <1499454199-31901-1-git-send-email-dinguyen@kernel.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a 'bypass-reg' binding property for the Stratix10 clock. There are quite a few clocks on the Stratix10 platform that have a separate bypass setting from the clock's original parent. The 'bypass-reg' binding contains the bypass register offset from the clock manager's base address and a bit index. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/clock/altr_socfpga.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index 1c32658..9e2754a 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -42,3 +42,6 @@ Optional properties: value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct hold/delay times that is needed for the SD/MMC CIU clock. The values of both can be 0-315 degrees, in 45 degree increments. +- bypass-reg : There are a few clocks on the Stratix10 platform that can be + bypassed from their original parents to a separate clock. This binding + property contains the bypass register and the bit index.