From patchwork Fri Jul 7 19:03:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 785720 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3x43sn5rkFz9s7C for ; Sat, 8 Jul 2017 05:03:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751659AbdGGTDY (ORCPT ); Fri, 7 Jul 2017 15:03:24 -0400 Received: from mail.kernel.org ([198.145.29.99]:46376 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750848AbdGGTDX (ORCPT ); Fri, 7 Jul 2017 15:03:23 -0400 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4209B22BD8; Fri, 7 Jul 2017 19:03:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4209B22BD8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dinguyen@kernel.org From: Dinh Nguyen To: robh+dt@kernel.org Cc: dinguyen@kernel.org, mark.rutland@arm.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCHv1 1/4] ARM: dts: socfpga: update documentation for clock bindings Date: Fri, 7 Jul 2017 14:03:16 -0500 Message-Id: <1499454199-31901-1-git-send-email-dinguyen@kernel.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update the bindings document for the Arria10 and Stratix10 clock bindings. Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/clock/altr_socfpga.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt index f72e80e..1c32658 100644 --- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt +++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt @@ -12,6 +12,20 @@ Required properties: "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and can get gated. + For Arria10: + "altr,socfpga-a10-pll-clock" - for a PLL clock + "altr,socfpga-a10-perip-clock" - The peripheral clock divided from the + PLL clock. + "altr,socfpga-a10-gate-clk" - Clocks that directly feed peripherals and + can get gated. + + For Stratix10: + "altr,socfpga-s10-pll-clock" - for a PLL clock + "altr,socfpga-s10-perip-clock" - The peripheral clock divided from the + PLL clock. + "altr,socfpga-s10-gate-clk" - Clocks that directly feed peripherals and + can get gated. + - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - clocks : shall be the input parent clock phandle for the clock. This is either an oscillator or a pll output.