From patchwork Fri Jun 23 13:00:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Yves MORDRET X-Patchwork-Id: 780014 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wvJbh4hQSz9sNW for ; Fri, 23 Jun 2017 23:05:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754525AbdFWNFO (ORCPT ); Fri, 23 Jun 2017 09:05:14 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:35547 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754075AbdFWNEO (ORCPT ); Fri, 23 Jun 2017 09:04:14 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5NCxKkV017491; Fri, 23 Jun 2017 15:01:11 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2b8d40xye7-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 23 Jun 2017 15:01:11 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E243134; Fri, 23 Jun 2017 13:01:10 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AECAA2407; Fri, 23 Jun 2017 13:01:10 +0000 (GMT) Received: from localhost (10.75.127.45) by SFHDAG5NODE2.st.com (10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1178.4; Fri, 23 Jun 2017 15:01:10 +0200 From: Pierre-Yves MORDRET To: Vinod Koul , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Russell King , Dan Williams , "M'boumba Cedric Madianga" , Fabrice GASNIER , Herbert Xu , Fabien DESSENNE , Amelie Delaunay , Pierre-Yves MORDRET , , , , Subject: [PATCH v2 1/5] dt-bindings: Document the STM32 DMAMUX bindings Date: Fri, 23 Jun 2017 15:00:49 +0200 Message-ID: <1498222853-11110-2-git-send-email-pierre-yves.mordret@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498222853-11110-1-git-send-email-pierre-yves.mordret@st.com> References: <1498222853-11110-1-git-send-email-pierre-yves.mordret@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG5NODE2.st.com (10.75.127.14) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-23_07:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the documentation of device tree bindings for the STM32 DMAMUX. Signed-off-by: M'boumba Cedric Madianga Signed-off-by: Pierre-Yves MORDRET --- Version history: v2: * Move clock bindings from optional to mandatory one * Drop channelID bindings as managed dynamically from now on by DMAMUX driver. --- --- .../devicetree/bindings/dma/stm32-dmamux.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt new file mode 100644 index 0000000..1d413c5 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt @@ -0,0 +1,57 @@ +STM32 DMA MUX (DMA request router) + +Required properties: +- compatible: "st,stm32-dmamux" +- reg: Memory map for accessing module +- #dma-cells: Should be set to <3>. + For more details about the three cells, please see + stm32-dma.txt documentation binding file +- dma-masters: Phandle pointing to the DMA controller + +Optional properties: +- dma-channels : Number of DMA channels supported. +- dma-requests : Number of DMA requests supported. +- resets: Reference to a reset controller asserting the DMA controller +- clocks: Input clock of the DMAMUX instance. + +Example: + +/* DMA controller */ +dma2: dma-controller@40026400 { + compatible = "st,stm32-dma"; + reg = <0x40026400 0x400>; + interrupts = <56>, + <57>, + <58>, + <59>, + <60>, + <68>, + <69>, + <70>; + clocks = <&clk_hclk>; + #dma-cells = <4>; + st,mem2mem; + resets = <&rcc 150>; + st,dmamux; + dma-channels = <8>; +}; + +/* DMA mux */ +dmamux2: dma-router@40020820 { + compatible = "st,stm32-dmamux"; + reg = <0x40020800 0x1c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma2>; +}; + +/* DMA client */ +usart1: serial@40011000 { + compatible = "st,stm32-usart", "st,stm32-uart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&clk_pclk2>; + dmas = <&dmamux2 41 0x414 0>, + <&dmamux2 42 0x414 0>; + dma-names = "rx", "tx"; +};