From patchwork Wed May 31 12:13:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 769082 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wd8Xg58stz9s78 for ; Wed, 31 May 2017 22:14:11 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RPotzuJr"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751108AbdEaMOJ (ORCPT ); Wed, 31 May 2017 08:14:09 -0400 Received: from mail-wm0-f42.google.com ([74.125.82.42]:35125 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751056AbdEaMOI (ORCPT ); Wed, 31 May 2017 08:14:08 -0400 Received: by mail-wm0-f42.google.com with SMTP id b84so116637503wmh.0 for ; Wed, 31 May 2017 05:14:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LWeBEfEnGKvUVu/ewZyG+wG3aYrhnXJxPc0p6ukn/ls=; b=RPotzuJrvQnfAuZXUezC2dX/n1h/rBcBsoC0OfKDtMLKBg1a9KbbleSoijfC2t3i5r clYINheL+FZhDQud5m+5ZK7AYYf4MfFhvAZ0ZnnsG2ScTKBnox0VhXIyzJWlM/XM6CLK HLz8ONExKL+OgFNmTXZUdNriCCr/j1YX4pzFs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LWeBEfEnGKvUVu/ewZyG+wG3aYrhnXJxPc0p6ukn/ls=; b=oNwh5mB3EvQg4d+w1FYcGuZKD0IF/a1LnirRDH6GJ6jhVamHZM09ZPeGltDTrCgBhA ULvB9fGgTNZq3o7/ig8oqZy73l63KJY7N/3zSfJsP20IEjIqoeRWm9tPJaOfwNzU+572 3aG/mihg3hgDmtkgqe7r4WMMT7GR7Bsx5kBWg8U6UBvQwvsG22HRduPBMxLv7asrG+wE 387rbGg6GqwNR1Hz1pBXMgLslgEmkmwrxl0Afact3Pt88fL6Dkf3ZASex9heWBY4OLv6 Yj2v5avo6lVEWzozI1KRoOvEyaFCHoOKHx+gZVHAUxJwZW3ndBG9eOelU7FSinH46aWC DCrQ== X-Gm-Message-State: AODbwcA1Yf7giNArRYM+vRgU16n3pZmjhwfb0eEJS3eaoRiek/DVQx3W ndlqW9UXnk8eQLJU X-Received: by 10.28.57.6 with SMTP id g6mr5433908wma.63.1496232846677; Wed, 31 May 2017 05:14:06 -0700 (PDT) Received: from lmenx321.st.com. ([80.215.231.254]) by smtp.gmail.com with ESMTPSA id z23sm2093823wrz.0.2017.05.31.05.14.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 May 2017 05:14:06 -0700 (PDT) From: Benjamin Gaignard To: yannick.fertre@st.com, alexandre.torgue@st.com, hverkuil@xs4all.nl, devicetree@vger.kernel.org, linux-media@vger.kernel.org, robh@kernel.org, hans.verkuil@cisco.com Cc: Benjamin Gaignard Subject: [PATCH v6 1/2] dt-bindings: media: stm32 cec driver Date: Wed, 31 May 2017 14:13:55 +0200 Message-Id: <1496232836-18220-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496232836-18220-1-git-send-email-benjamin.gaignard@linaro.org> References: <1496232836-18220-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings documentation for stm32 CEC driver. Signed-off-by: Benjamin Gaignard Acked-by: Rob Herring --- .../devicetree/bindings/media/st,stm32-cec.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-cec.txt diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt new file mode 100644 index 0000000..6be2381 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.txt @@ -0,0 +1,19 @@ +STMicroelectronics STM32 CEC driver + +Required properties: + - compatible : value should be "st,stm32-cec" + - reg : Physical base address of the IP registers and length of memory + mapped region. + - clocks : from common clock binding: handle to CEC clocks + - clock-names : from common clock binding: must be "cec" and "hdmi-cec". + - interrupts : CEC interrupt number to the CPU. + +Example for stm32f746: + +cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; +};