From patchwork Tue May 30 09:16:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 768508 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wcShZ073Gz9s65 for ; Tue, 30 May 2017 19:18:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751485AbdE3JQc (ORCPT ); Tue, 30 May 2017 05:16:32 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:44746 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751454AbdE3JQa (ORCPT ); Tue, 30 May 2017 05:16:30 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 9721920ED9; Tue, 30 May 2017 11:16:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 706B720411; Tue, 30 May 2017 11:16:28 +0200 (CEST) From: Thomas Petazzoni To: Thomas Gleixner , Jason Cooper , Marc Zyngier , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-arm-kernel@lists.infradead.org, Nadav Haklai , Hanna Hawa , Yehuda Yitschak , Antoine Tenart , Thomas Petazzoni Subject: [PATCH 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP Date: Tue, 30 May 2017 11:16:06 +0200 Message-Id: <1496135772-20694-2-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1496135772-20694-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the Device Tree binding documentation for the Marvell GICP, an extension to the GIC that allows to trigger GIC SPI interrupts using memory transactions. It is used by the ICU unit in the Marvell CP110 block to turn wired interrupts inside the CP into SPI interrupts at the GIC level in the AP. Signed-off-by: Thomas Petazzoni --- .../bindings/interrupt-controller/marvell,gicp.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt new file mode 100644 index 0000000..996bdbf --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt @@ -0,0 +1,20 @@ +Marvell GICP Controller +----------------------- + +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI +interrupts by doing a memory transaction. It is used by the ICU +located in the Marvell CP110 to turn wired interrupts inside the CP +into GIC SPI interrupts. + +Required properties: + +- compatible: Must be "marvell,gicp" + +- reg: Must be the address and size of the GICP SPI registers + +Example: + +gicp_spi: gicp-spi@3f0040 { + compatible = "marvell,gicp"; + reg = <0x3f0040 0x10>; +};