From patchwork Mon May 22 12:48:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 765388 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wWd3L2p8bz9s7t for ; Mon, 22 May 2017 22:18:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757890AbdEVMRz (ORCPT ); Mon, 22 May 2017 08:17:55 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6795 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759419AbdEVMRw (ORCPT ); Mon, 22 May 2017 08:17:52 -0400 Received: from 172.30.72.55 (EHLO dggeml405-hub.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APA29797; Mon, 22 May 2017 20:17:17 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml405-hub.china.huawei.com (10.3.17.49) with Microsoft SMTP Server id 14.3.301.0; Mon, 22 May 2017 20:17:08 +0800 From: Shaokun Zhang To: , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v8 2/9] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Djtag dts bindings Date: Mon, 22 May 2017 20:48:14 +0800 Message-ID: <1495457294-233366-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5922D6CE.008D, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 68d9c1467c85bad33c42a0ddcbf779c9 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tan Xiaojun Add Hisilicon HiP05/06/07 Djtag dts bindings for CPU and IO Die Signed-off-by: Tan Xiaojun Signed-off-by: Anurup M Acked-by: Rob Herring --- .../devicetree/bindings/arm/hisilicon/djtag.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/djtag.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt new file mode 100644 index 0000000..fde5bab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/djtag.txt @@ -0,0 +1,51 @@ +The Hisilicon Djtag is an independent component which connects with some other +components in the SoC by Debug Bus. The djtag is available in CPU and IO dies +in the chip. The djtag controls access to connecting modules of CPU and IO +dies. +The various connecting components in CPU die (like L3 cache, L3 cache PMU etc.) +are accessed by djtag during real time debugging. In IO die there are connecting +components like RSA. These components appear as devices attached to djtag bus. + +Hisilicon HiP05/06/07 djtag for CPU die +Required properties: + - compatible : The value should be as follows + (a) "hisilicon,hip05-cpu-djtag-v1" for CPU die which use v1 hw in + HiP05 chipset. + (b) "hisilicon,hip06-cpu-djtag-v1" for CPU die which use v1 hw in + HiP06 chipset. + (c) "hisilicon,hip07-cpu-djtag-v2" for CPU die which use v2 hw in + HiP07 chipset. + - reg : Register address and size + - hisilicon,scl-id : The Super Cluster ID for CPU or IO die + +Example 1: Djtag for CPU die in HiP07 + + /* for Hisilicon HiP07 djtag for CPU Die */ + djtag0: djtag@60010000 { + compatible = "hisilicon,hip07-cpu-djtag-v2"; + reg = <0x0 0x60010000 0x0 0x10000>; + hisilicon,scl-id = <0x03>; + + /* All connecting components will appear as child nodes */ + }; + +Hisilicon HiP05/06/07 djtag for IO die +Required properties: + - compatible : The value should be as follows + (a) "hisilicon,hip05-io-djtag-v1" for IO die which use v1 hw in + HiP05 chipset. + (c) "hisilicon,hip06-io-djtag-v2" for IO die which use v2 hw in + HiP06 chipset. + (d) "hisilicon,hip07-io-djtag-v2" for IO die which use v2 hw in + HiP07 chipset + +Example 2: Djtag for IO die in HiP05 + + /* for Hisilicon HiP05 djtag for IO Die */ + djtag1: djtag@d0000000 { + compatible = "hisilicon,hip05-io-djtag-v1"; + reg = <0x0 0xd0000000 0x0 0x10000>; + hisilicon,scl-id = <0x0>; + + /* All connecting components will appear as child nodes */ + };