From patchwork Tue May 16 12:56:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 762994 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wRyCW2t76z9ryT for ; Tue, 16 May 2017 22:57:27 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="AWKow71u"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751219AbdEPM5Z (ORCPT ); Tue, 16 May 2017 08:57:25 -0400 Received: from mail-wm0-f47.google.com ([74.125.82.47]:34930 "EHLO mail-wm0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752228AbdEPM5W (ORCPT ); Tue, 16 May 2017 08:57:22 -0400 Received: by mail-wm0-f47.google.com with SMTP id b84so132413258wmh.0 for ; Tue, 16 May 2017 05:57:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RL2hNK40M/Pp+393pxYEstSZq5Zv3Y8SrfXaQXFZybk=; b=AWKow71uslzT7sCKVq5sAWccTUnFEWlQnxthQ2cMKxMPjfw7jkyM/LZBEGKpn4JCby vX3xFqtNMZyZfAbxi5oZVqqY952Zd8ZrkJBBJ9GR397Cqd8m5HzSqR/dKtMTLdvRzqGh FcWNj9PrP3ej5OfSzTL41Kz0ZvWxvK1cQXG18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RL2hNK40M/Pp+393pxYEstSZq5Zv3Y8SrfXaQXFZybk=; b=X6iMSfK/W4RjUEvYLZN2NT/i/K1YfuwbNo/sagzyFUeFdmvFemb1md8q9OoO9pGubU qXHD57LP/edvkDLHU550KH1b1wLDFOXGR43vZ4A1t+6GbWDzAo4EmkkvdcRPgeXhLlTQ KV5EkOZI7EBcxzNBkEiJ5r4J60Me7/Mjx9ujtK7Bjh9gjRweoRVj1xQkpT83cOtZ56YA OZE9eN5FkaELXODTaaZ5X0gRErNH9n9AoT2tnux/9cXsMZh6InCCQ7bio0EUB9np3EGJ F67KOnJJaLBuhpq0VJ+7HZdUvA+lb8GDU74Y+AtSVRPfESQcNXi8GM+9qPcTKtB0fJJP a/WA== X-Gm-Message-State: AODbwcATLZvq8jsUaylWUXGjPocL4agmt/UwshnlA9/+Qp7QPbVIwh88 ycHaPaoVoautX8Gc X-Received: by 10.28.151.197 with SMTP id z188mr6758828wmd.58.1494939441247; Tue, 16 May 2017 05:57:21 -0700 (PDT) Received: from lmenx321.st.com. ([80.214.124.106]) by smtp.gmail.com with ESMTPSA id w96sm2288567wrc.14.2017.05.16.05.57.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 05:57:20 -0700 (PDT) From: Benjamin Gaignard To: yannick.fertre@st.com, alexandre.torgue@st.com, hverkuil@xs4all.nl, devicetree@vger.kernel.org, linux-media@vger.kernel.org, robh@kernel.org, hans.verkuil@cisco.com Cc: Benjamin Gaignard Subject: [PATCH v2 1/2] binding for stm32 cec driver Date: Tue, 16 May 2017 14:56:22 +0200 Message-Id: <1494939383-18937-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494939383-18937-1-git-send-email-benjamin.gaignard@linaro.org> References: <1494939383-18937-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/media/st,stm32-cec.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-cec.txt diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt new file mode 100644 index 0000000..6be2381 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.txt @@ -0,0 +1,19 @@ +STMicroelectronics STM32 CEC driver + +Required properties: + - compatible : value should be "st,stm32-cec" + - reg : Physical base address of the IP registers and length of memory + mapped region. + - clocks : from common clock binding: handle to CEC clocks + - clock-names : from common clock binding: must be "cec" and "hdmi-cec". + - interrupts : CEC interrupt number to the CPU. + +Example for stm32f746: + +cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; +};