From patchwork Tue May 16 09:01:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 762843 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wRrzR4QSJz9s85 for ; Tue, 16 May 2017 19:01:39 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="bDFUJHOb"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751991AbdEPJBh (ORCPT ); Tue, 16 May 2017 05:01:37 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:37722 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751943AbdEPJBf (ORCPT ); Tue, 16 May 2017 05:01:35 -0400 Received: by mail-wm0-f41.google.com with SMTP id d127so111520781wmf.0 for ; Tue, 16 May 2017 02:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RL2hNK40M/Pp+393pxYEstSZq5Zv3Y8SrfXaQXFZybk=; b=bDFUJHObj9DCyZoWhem4zd110iBvn/lKIA4fvWgU/LN+/ezOr4kGQaPFy0RQVAm0vZ O6n9tZjuCDpH/ZAsW8gbuk65S3TIgUVKAHqIpRRDOaeGtvK+OeuLz8c6+j+mc+CKyfoG 1fSeNPAAmScgAHdo6V0zkvvEPU2dT8v5iyjc8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RL2hNK40M/Pp+393pxYEstSZq5Zv3Y8SrfXaQXFZybk=; b=Mk4yarROPWBAeICZYlJfHPoYkaCffTQ8AkQtnkBAat6o4356WmqG/Juad78kyhaE3E V2BJGnS7M2t9lwD532CHV83Joqqc58rymHTieCzOe7On2dP91rRXByFLlI8iZr/o2Ls9 p6Dy3bTA2uxqphm0GMpBKMAJASKSpbmONKae4vxA2pULFss/xE7oHMGt6+D+IOdU2e9M 0E731I+imbAcvZzJu9WFk8u15hIWaRzHaXqQZn5zx0w6PFlRyvimrP0R+xcgTmIXRfqj NfCU/oeywRB90MzReSst4TnOrGYNpXdGagit0VLWB16aC7OCqDCTe5Zs9oNTyGorEcoR NDFg== X-Gm-Message-State: AODbwcDGRp5fjegQD363yB8XkOLynRD1ccocWVL4UTqAkMN2LhpRx3dO qF9gW1sf0ztPwk3C X-Received: by 10.28.154.86 with SMTP id c83mr6786545wme.94.1494925294365; Tue, 16 May 2017 02:01:34 -0700 (PDT) Received: from lmenx321.st.com. ([80.215.37.242]) by smtp.gmail.com with ESMTPSA id x17sm1023436wrd.63.2017.05.16.02.01.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 May 2017 02:01:33 -0700 (PDT) From: Benjamin Gaignard To: yannick.ferte@st.com, alexandre.torgue@st.com, hverkuil@xs4all.nl, devicetree@vger.kernel.org, linux-media@vger.kernel.org, robh@kernel.org, hans.verkuil@cisco.com Cc: Benjamin Gaignard Subject: [PATCH 1/2] binding for stm32 cec driver Date: Tue, 16 May 2017 11:01:19 +0200 Message-Id: <1494925280-4527-2-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1494925280-4527-1-git-send-email-benjamin.gaignard@linaro.org> References: <1494925280-4527-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/media/st,stm32-cec.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32-cec.txt diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.txt b/Documentation/devicetree/bindings/media/st,stm32-cec.txt new file mode 100644 index 0000000..6be2381 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32-cec.txt @@ -0,0 +1,19 @@ +STMicroelectronics STM32 CEC driver + +Required properties: + - compatible : value should be "st,stm32-cec" + - reg : Physical base address of the IP registers and length of memory + mapped region. + - clocks : from common clock binding: handle to CEC clocks + - clock-names : from common clock binding: must be "cec" and "hdmi-cec". + - interrupts : CEC interrupt number to the CPU. + +Example for stm32f746: + +cec: cec@40006c00 { + compatible = "st,stm32-cec"; + reg = <0x40006C00 0x400>; + interrupts = <94>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; + clock-names = "cec", "hdmi-cec"; +};