From patchwork Mon Apr 17 21:49:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 751567 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w6MJn64bFz9s3w for ; Tue, 18 Apr 2017 07:46:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755843AbdDQVqA (ORCPT ); Mon, 17 Apr 2017 17:46:00 -0400 Received: from mga05.intel.com ([192.55.52.43]:29253 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755714AbdDQVp7 (ORCPT ); Mon, 17 Apr 2017 17:45:59 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 17 Apr 2017 14:45:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.37,217,1488873600"; d="scan'208"; a="1157226700" Received: from tthayer-hp-z620-ubuntu.an.intel.com (HELO tthayer-HP-Z620-Ubuntu.altera.com) ([10.122.105.144]) by fmsmga002.fm.intel.com with ESMTP; 17 Apr 2017 14:45:57 -0700 From: thor.thayer@linux.intel.com To: wsa@the-dreams.de, robh@kernel.org Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, thor.thayer@linux.intel.com Subject: [PATCHv2 2/3] dt-bindings: i2c: Add Altera I2C Controller Date: Mon, 17 Apr 2017 16:49:02 -0500 Message-Id: <1492465743-8679-3-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1492465743-8679-1-git-send-email-thor.thayer@linux.intel.com> References: <1492465743-8679-1-git-send-email-thor.thayer@linux.intel.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thor Thayer Add the documentation to support the Altera synthesizable logic I2C Controller. Signed-off-by: Thor Thayer --- v2 Change the subject to identify dt-bindings Add synthesizable logic to description. Change compatible string to "altr,softip-i2c" Make description of clock phandle singular since 1 clock. Remove altr, from fifo-size Specify fifo-size is in bytes. --- .../devicetree/bindings/i2c/i2c-altera.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-altera.txt diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt new file mode 100644 index 0000000..ba25b1ea --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-altera.txt @@ -0,0 +1,38 @@ +* Altera I2C Controller +* This is Altera's synthesizable logic block I2C Controller. + +Required properties : + - compatible : should be "altr,softip-i2c" + - reg : Offset and length of the register set for the device + - interrupts : where IRQ is the interrupt number. + - clocks : phandle to input clock. + - #address-cells = <1>; + - #size-cells = <0>; + +Recommended properties : + - clock-frequency : desired I2C bus clock frequency in Hz. + +Optional properties : + - fifo-size : Size of the RX and TX FIFOs in bytes. + - Child nodes conforming to i2c bus binding + +Example : + + i2c@100080000 { + compatible = "altr,softip-i2c"; + reg = <0x00000001 0x00080000 0x00000040>; + interrupt-parent = <&intc>; + interrupts = <0 43 4>; + clocks = <&clk_0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + fifo-size = <4>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + }; +