From patchwork Sun Apr 9 17:10:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Moritz Fischer X-Patchwork-Id: 748761 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w1Kb10cpLz9s65 for ; Mon, 10 Apr 2017 03:10:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752322AbdDIRKv (ORCPT ); Sun, 9 Apr 2017 13:10:51 -0400 Received: from mail.kernel.org ([198.145.29.136]:42228 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752298AbdDIRKu (ORCPT ); Sun, 9 Apr 2017 13:10:50 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C626620357; Sun, 9 Apr 2017 17:10:48 +0000 (UTC) Received: from tyrael.amer.corp.natinst.com (207-114-172-147.static.twtelecom.net [207.114.172.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8968220303; Sun, 9 Apr 2017 17:10:47 +0000 (UTC) From: Moritz Fischer To: linux-fpga@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, robh+dt@kernel.org, Moritz Fischer , Michal Simek , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= Subject: [PATCH v5] dt-bindings: fpga: Add bindings document for Xilinx LogiCore PR Decoupler Date: Sun, 9 Apr 2017 10:10:31 -0700 Message-Id: <1491757831-10510-1-git-send-email-mdf@kernel.org> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer Signed-off-by: Michal Simek Acked-by: Alan Tull Cc: Sören Brinkmann Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Rob Herring --- Changes from v4: - Ssubject line - Replaced 'or' by 'followed by' as suggested by Rob Changes from v3: - Addressed Michal's comments - Addressed Alan's Comments - Added Alan's Acked-by Changes from v2: - Added refence to generic fpga-region bindings - Fixed up reg property in example - Added fallback to "xlnx,pr-decoupler" without version Changes from v1: - Added clock names & clock to example - Merged some of the description from Michal's version --- .../bindings/fpga/xilinx-pr-decoupler.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file mode 100644 index 0000000..b2c58fb --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt @@ -0,0 +1,36 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouplers which can be handled independently or chained via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by + "xlnx,pr-decoupler" +- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings. + +Example: + fpga-bridge@100000450 { + compatible = "xlnx,pr-decoupler-1.00", + "xlnx-pr-decoupler"; + regs = <0x10000045 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + };