From patchwork Thu Apr 6 05:51:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 747603 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vzBfv5qLHz9s85 for ; Thu, 6 Apr 2017 15:51:51 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="pFP+ixOR"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="pFP+ixOR"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752211AbdDFFvs (ORCPT ); Thu, 6 Apr 2017 01:51:48 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42226 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756191AbdDFFvm (ORCPT ); Thu, 6 Apr 2017 01:51:42 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BC94160DA6; Thu, 6 Apr 2017 05:51:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1491457901; bh=dx6Q2/oMEplfAtjJ8fdE6StQmOgjAygXpWhUOhS60s4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pFP+ixOR1VN8pcUWA7ozWRByg4nEH4A62rV3IAhLXM6s7nFiWl3GWt/b9wQ3bMIPh GG2BFITuJQbx0iJD1ycFaQXNNVGEhJigxgZgiTKpg2O8NaULWhOTx8AHfZMQ0bdG0+ 0hmwZPvWIN595xSzUr7+d/Z+KW/iDUGcsCJfc0x0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-41.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8C7D660D8E; Thu, 6 Apr 2017 05:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1491457901; bh=dx6Q2/oMEplfAtjJ8fdE6StQmOgjAygXpWhUOhS60s4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pFP+ixOR1VN8pcUWA7ozWRByg4nEH4A62rV3IAhLXM6s7nFiWl3GWt/b9wQ3bMIPh GG2BFITuJQbx0iJD1ycFaQXNNVGEhJigxgZgiTKpg2O8NaULWhOTx8AHfZMQ0bdG0+ 0hmwZPvWIN595xSzUr7+d/Z+KW/iDUGcsCJfc0x0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 8C7D660D8E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: kishon@ti.com, robh+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, mark.rutland@arm.com, sboyd@codeaurora.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, Vivek Gautam Subject: [PATCH V8 1/4] dt-bindings: phy: Add support for QUSB2 phy Date: Thu, 6 Apr 2017 11:21:22 +0530 Message-Id: <1491457885-5254-2-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1491457885-5254-1-git-send-email-vivek.gautam@codeaurora.org> References: <1491457885-5254-1-git-send-email-vivek.gautam@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm chipsets have QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller. Adding dt binding information for the same. Signed-off-by: Vivek Gautam Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Changes since v7: - None, just added Stephen's Reviewed-by tag. Changes since v6: - Dropped 'vdd-phy-supply' that used pm8994_s2 regulator, from bindings. As Stephen said, the pm8994_s2 is a 'corner' regulator and it shouldn't be right to put it as a regulator supply. Work is in progress to handle these sort of power supplies. Changes since v5: - Removed leading 0 from the address in 'reg' property. Changes since v4: - None. Changes since v3: - Added 'Acked-by' from Rob. - Removed 'reset-names' and 'nvmem-cell-names' from the bindings since we use only one cell. Changes since v2: - Removed binding for "ref_clk_src" since we don't request this clock in the driver. - Addressed s/vdda-phy-dpdm/vdda-phy-dpdm-supply. - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names. - Addressed s/tune2_hstx_trim_efuse/tune2_hstx_trim. Don't need to add 'efuse' suffix to nvmem cell. - Addressed s/qusb2phy/phy for the node name. Changes since v1: - New patch, forked out of the original driver patch: "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips" - Updated dt bindings to remove 'hstx-trim-bit-offset' and 'hstx-trim-bit-len' bindings. .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt new file mode 100644 index 000000000000..aa0fcb05acb3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt @@ -0,0 +1,43 @@ +Qualcomm QUSB2 phy controller +============================= + +QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +Required properties: + - compatible: compatible list, contains "qcom,msm8996-qusb2-phy". + - reg: offset and length of the PHY register set. + - #phy-cells: must be 0. + + - clocks: a list of phandles and clock-specifier pairs, + one for each entry in clock-names. + - clock-names: must be "cfg_ahb" for phy config clock, + "ref" for 19.2 MHz ref clk, + "iface" for phy interface clock (Optional). + + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. + - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals. + + - resets: Phandle to reset to phy block. + +Optional properties: + - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim' + tuning parameter value for qusb2 phy. + + - qcom,tcsr-syscon: Phandle to TCSR syscon register region. + +Example: + hsusb_phy: phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x7411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>, + clock-names = "cfg_ahb", "ref"; + + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2p_hstx_trim>; + };