Message ID | 1489711910-17443-1-git-send-email-mdf@kernel.org |
---|---|
State | Superseded, archived |
Headers | show |
On 17.3.2017 01:51, Moritz Fischer wrote: > This adds the binding documentation for the Xilinx LogiCORE PR > Decoupler soft core. > > Signed-off-by: Moritz Fischer <mdf@kernel.org> > Cc: Michal Simek <michal.simek@xilinx.com> > Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> > Cc: linux-kernel@vger.kernel.org > Cc: devicetree@vger.kernel.org > --- > > Changes from v1: > - Added clock names & clock to example > - Merged some of the description from Michal's version > > --- > .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > new file mode 100644 > index 0000000..2080006 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > @@ -0,0 +1,32 @@ > +Xilinx LogiCORE Partial Reconfig Decoupler Softcore > + > +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more > +decouplers / fpga bridges. > +The controller can decouple/disable the bridges which prevents signal > +changes from passing through the bridge. The controller can also > +couple / enable the bridges which allows traffic to pass through the > +bridge normally. > + > +The Driver supports only MMIO handling. A PR region can have multiple > +PR Decouples which can bhe handled independently or chaines via decouple/ > +decouple_status signals. > + > +Required properties: > +- compatible : Should contain "xlnx,pr-decoupler-1.00" should I would tend to do this as "xlnx,pr-decoupler-1.00" and/or "xlnx,pr_decoupler" > +- regs : base address and size for decoupler module > +- clocks : input clock to IP > +- clock-names : should contain "aclk" > + > +Optional properties: > +- bridge-enable : 0 if driver should disable bridge at startup > + 1 if driver should enable bridge at startup > + Default is to leave bridge in current state. Interesting that this is not a bool. But anyway this should be link to bridge binding because I expect this is the same for all. > + > +Example: > + fpga-bridge@100000450 { > + compatible = "xlnx,pr-decoupler-1.00"; "xlnx,pr-decoupler-1.00", "xlnx,pr_decoupler"; > + regs = <0x1000 0x10>; > + clocks = <&clkc 15>; > + clock-names = "aclk"; > + bridge-enable = <0>; > + }; > Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 17.3.2017 01:51, Moritz Fischer wrote: > This adds support for the Xilinx LogiCORE PR Decoupler > soft-ip that does decoupling of PR regions in the FPGA > fabric during partial reconfiguration. > > Signed-off-by: Moritz Fischer <mdf@kernel.org> > Cc: Michal Simek <michal.simek@xilinx.com> > Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> > Cc: linux-kernel@vger.kernel.org > Cc: devicetree@vger.kernel.org > --- > > Changes from v1: > - Added Michal as Co-Author since I pulled in some of his code > - Reworked clk handling in _remove() > - Pulled in Michal's version of show_enable(), ditched priv->enabled > > --- > drivers/fpga/Kconfig | 9 +++ > drivers/fpga/Makefile | 1 + > drivers/fpga/xilinx-pr-decoupler.c | 147 +++++++++++++++++++++++++++++++++++++ > 3 files changed, 157 insertions(+) > create mode 100644 drivers/fpga/xilinx-pr-decoupler.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 967cda4..e42c7dc 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -69,6 +69,15 @@ config ALTERA_FREEZE_BRIDGE > isolate one region of the FPGA from the busses while that > region is being reprogrammed. > > +config XILINX_PR_DECOUPLER > + tristate "Xilinx LogiCORE PR Decoupler" > + depends on FPGA_BRIDGE > + help > + Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. > + The PR Decoupler exists in the FPGA fabric to isolate one > + region of the FPGA from the busses while that region is > + being reprogrammed during partial reconfig. > + > endif # FPGA > > endmenu > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index cc0d364..3f04bcf 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -15,6 +15,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o > +obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o > > # High Level Interfaces > obj-$(CONFIG_FPGA_REGION) += fpga-region.o > diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c > new file mode 100644 > index 0000000..761700c > --- /dev/null > +++ b/drivers/fpga/xilinx-pr-decoupler.c > @@ -0,0 +1,147 @@ > +/* > + * Copyright (c) 2017, National Instruments Corp. > + * Copyright (c) 2017, Xilix Inc > + * > + * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration > + * Decoupler IP Core. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/of_device.h> > +#include <linux/module.h> > +#include <linux/fpga/fpga-bridge.h> > + > +#define CTRL_CMD_DECOUPLE BIT(0) > +#define CTRL_CMD_COUPLE ~BIT(0) > + > +struct xlnx_pr_decoupler_data { > + void __iomem *io_base; > + struct clk *clk; > +}; > + > +static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable) > +{ > + int err; > + struct xlnx_pr_decoupler_data *priv = bridge->priv; > + > + err = clk_enable(priv->clk); > + if (err) > + return err; > + > + if (enable) > + writel(CTRL_CMD_COUPLE, priv->io_base); > + else > + writel(CTRL_CMD_DECOUPLE, priv->io_base); > + > + clk_disable(priv->clk); > + > + return 0; > +} > + > +static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge) > +{ > + const struct xlnx_pr_decoupler_data *priv = bridge->priv; > + u32 status; > + int err; > + > + err = clk_enable(priv->clk); > + if (err) > + return err; > + > + status = readl(priv->io_base); > + > + clk_disable(priv->clk); > + > + return !status; > +} > + > +static struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = { > + .enable_set = xlnx_pr_decoupler_enable_set, > + .enable_show = xlnx_pr_decoupler_enable_show, > +}; > + > +static const struct of_device_id xlnx_pr_decoupler_of_match[] = { > + { .compatible = "xlnx,pr-decoupler-1.00", }, I would add here that generic compatible string too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file mode 100644 index 0000000..2080006 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt @@ -0,0 +1,32 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouples which can bhe handled independently or chaines via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00" +- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + fpga-bridge@100000450 { + compatible = "xlnx,pr-decoupler-1.00"; + regs = <0x1000 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + };
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org --- Changes from v1: - Added clock names & clock to example - Merged some of the description from Michal's version --- .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt