From patchwork Tue Mar 14 11:04:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 738640 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vjBjs1Dzsz9s2Q for ; Tue, 14 Mar 2017 22:05:53 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="sdBQOA3J"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751080AbdCNLFl (ORCPT ); Tue, 14 Mar 2017 07:05:41 -0400 Received: from mail-wr0-f182.google.com ([209.85.128.182]:36612 "EHLO mail-wr0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750860AbdCNLFD (ORCPT ); Tue, 14 Mar 2017 07:05:03 -0400 Received: by mail-wr0-f182.google.com with SMTP id u108so121344754wrb.3 for ; Tue, 14 Mar 2017 04:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MKynRj7dMOO8BHsAnmREyKxT7WMtmSwyTx8D5lV6lrA=; b=sdBQOA3JYkOF6NKkhMh9Y9X/U22tRvROcom9Ja89Rbj8NHf3JydkqUGZJqftD9jr55 9xRLO+O4iyp1+yFjYX0S3h4o5c08Ude6B/+WWC9T13RYo7/+CjM4RsBjI1iJurFcSMV4 9vz8HuBKyyC8jfIXmf8NhTIWVlzMje4KsQoRIvoGCUkZusMm80YPOnIqDKGIdPf2jTa6 nl80lhK0zbRgtRhRs+qfRPhG7s7FfglC2S0BQ29207HwD9MVXK1k+d/Bf4ccUsvYttV7 2AHKfZgEwSMpOpi2qZqAI/Xt6SGmuHblioosNc/e7WE5ai9ROUWBmfoLGFgmioDaNJOB TeFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MKynRj7dMOO8BHsAnmREyKxT7WMtmSwyTx8D5lV6lrA=; b=sAJbjGeWqojeGovP51sMXwXAU6YOIRgQ3IgZnad9Nyx4SM5ySXGVvQKSHeUpFeVJd6 oUjTdSrlS6lVTPJbkuoPiq1nMv7666O6XA0GqcZbKV4zFB6uDcereZTAeCHJNOEA7H2v frvEJAHC+JavrGh4LJD1JOpFU2PjbTfO1wDErTHsinT9IHxBGSM5HL5KtphYd0a7eRyf nMXPNamey1KrX2CBo8Hfn2im/grF+2uOWMoyY39gcYfDxBgu1Bel9YEgnJMTqpzol/E4 Mxdass6rwBD5q/UDeFON6nsP9F17G4zA9pSl7AQKYLvOPXtJkJAcaGIRQZ6I1Q2f3CZI eIvg== X-Gm-Message-State: AMke39lV7kveFIBxSvM2brBf0QieH4zJlEjFQnuaLLdqxE7r+UHjdyD78UMutPYAFXmDXuxh X-Received: by 10.223.150.110 with SMTP id c43mr32226358wra.85.1489489501557; Tue, 14 Mar 2017 04:05:01 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id g6sm14962144wmc.30.2017.03.14.04.05.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Mar 2017 04:05:01 -0700 (PDT) From: Bartosz Golaszewski To: Tejun Heo , Rob Herring , Mark Rutland , Neil Armstrong , Michael Turquette , Kevin Hilman , Patrick Titiano , Tony Lindgren , Sergei Shtylyov Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH v2 1/2] dt-bindings: ata: add DT bindings for ahci-dm816 SATA controller Date: Tue, 14 Mar 2017 12:04:50 +0100 Message-Id: <1489489491-14195-2-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1489489491-14195-1-git-send-email-bgolaszewski@baylibre.com> References: <1489489491-14195-1-git-send-email-bgolaszewski@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings for the onboard SATA controller present on the DM816x SoCs. Signed-off-by: Bartosz Golaszewski Acked-by: Rob Herring --- .../devicetree/bindings/ata/ahci-dm816.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-dm816.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-dm816.txt b/Documentation/devicetree/bindings/ata/ahci-dm816.txt new file mode 100644 index 0000000..f8c535f --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-dm816.txt @@ -0,0 +1,21 @@ +Device tree binding for the TI DM816 AHCI SATA Controller +--------------------------------------------------------- + +Required properties: + - compatible: must be "ti,dm816-ahci" + - reg: physical base address and size of the register region used by + the controller (as defined by the AHCI 1.1 standard) + - interrupts: interrupt specifier (refer to the interrupt binding) + - clocks: list of phandle and clock specifier pairs (or only + phandles for clock providers with '0' defined for + #clock-cells); two clocks must be specified: the functional + clock and an external reference clock + +Example: + + sata: sata@4a140000 { + compatible = "ti,dm816-ahci"; + reg = <0x4a140000 0x10000>; + interrupts = <16>; + clocks = <&sysclk5_ck>, <&sata_refclk>; + };