From patchwork Thu Mar 9 09:07:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 736906 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vf4P76D5Qz9s7B for ; Thu, 9 Mar 2017 20:10:35 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="ZLiTJqZN"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="ZLiTJqZN"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753704AbdCIJIw (ORCPT ); Thu, 9 Mar 2017 04:08:52 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:49916 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752790AbdCIJI3 (ORCPT ); Thu, 9 Mar 2017 04:08:29 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id DAFAD6077D; Thu, 9 Mar 2017 09:07:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1489050466; bh=dskmW+VhNpCnG+fPHNyyBBPErD1yqwDri6ukWDiYveA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZLiTJqZNvyRe3fCZ/VngC4TR3HCVpPlbfd0aeOyF7/zYgVKGFY9I0XKfdg1gKpsMD UQSTDEOze2r5SzGMsyuW0oaMft6XJpB2EzyVg0BkWHvjRT8AONwveOlN3p0P9hn//F TIuJnmu/oGzBpwLrJjc6e5aI9c3UtrOSMtqBN8zQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-41.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id DBC3060723; Thu, 9 Mar 2017 09:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1489050466; bh=dskmW+VhNpCnG+fPHNyyBBPErD1yqwDri6ukWDiYveA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZLiTJqZNvyRe3fCZ/VngC4TR3HCVpPlbfd0aeOyF7/zYgVKGFY9I0XKfdg1gKpsMD UQSTDEOze2r5SzGMsyuW0oaMft6XJpB2EzyVg0BkWHvjRT8AONwveOlN3p0P9hn//F TIuJnmu/oGzBpwLrJjc6e5aI9c3UtrOSMtqBN8zQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org DBC3060723 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: robh+dt@kernel.org, kishon@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, sboyd@codeaurora.org, bjorn.andersson@linaro.org, srinivas.kandagatla@linaro.org, Vivek Gautam , Rob Herring Subject: [PATCH v5 3/4] dt-bindings: phy: Add support for QMP phy Date: Thu, 9 Mar 2017 14:37:20 +0530 Message-Id: <1489050441-3240-4-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489050441-3240-1-git-send-email-vivek.gautam@codeaurora.org> References: <1489050441-3240-1-git-send-email-vivek.gautam@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm chipsets have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Adding dt binding information for the same. Signed-off-by: Vivek Gautam Cc: Rob Herring Acked-by: Rob Herring --- Hi Rob, I have removed your Acked-by tag because of the change in bindings. Please consider adding your Ack again if you are fine with these updated bindings. Changes since v4: - Added bindings for child nodes. Each phy lane is represented by child node with its own register space (for tx, rx and pcs blocks), and clocks and resets for power control facility. - Removed register space and lane offsets for tx, rx and pcs blocks from qmp phy node. - #phy-cells is now part of each child node and thus must be 0. - Added information on list of mandatory clocks and resets for each phy. Changes since v3: - Added #clock-cells = <1>, indicating that phy is a clock provider. Changes since v2: - Removed binding for "ref_clk_src" since we don't request this clock in the driver. - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names. - Using 'phy' for the node name. Changes since v1: - New patch, forked out of the original driver patch: "phy: qcom-qmp: new qmp phy driver for qcom-chipsets" - Added 'Acked-by' from Rob. - Updated bindings to include mem resource as a list of offset - length pair for serdes block and for each lane. - Added a new binding for 'lane-offsets' that contains offsets to tx, rx and pcs blocks from each lane base address. .../devicetree/bindings/phy/qcom-qmp-phy.txt | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt new file mode 100644 index 000000000000..5595c3fabe0a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -0,0 +1,106 @@ +Qualcomm QMP PHY controller +=========================== + +QMP phy controller supports physical layer functionality for a number of +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +Required properties: + - compatible: compatible list, contains: + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. + + - reg: offset and length of register set for PHY's common serdes block. + + - #clock-cells: must be 1 + - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe + interface (for pipe based PHYs). These clock are then gate-controlled + by gcc. + - #address-cells: must be 1 + - #size-cells: must be 1 + - ranges: must be present + + - clocks: a list of phandles and clock-specifier pairs, + one for each entry in clock-names. + - clock-names: "cfg_ahb" for phy config clock, + "aux" for phy aux clock, + "ref" for 19.2 MHz ref clk, + For "qcom,msm8996-qmp-pcie-phy" must contain: + "aux", "cfg_ahb", "ref". + For "qcom,msm8996-qmp-usb3-phy" must contain: + "aux", "cfg_ahb", "ref". + + - resets: a list of phandles and reset controller specifier pairs, + one for each entry in reset-names. + - reset-names: "phy" for reset of phy block, + "common" for phy common block reset, + "cfg" for phy's ahb cfg block reset (Optional). + For "qcom,msm8996-qmp-pcie-phy" must contain: + "phy", "common", "cfg". + For "qcom,msm8996-qmp-usb3-phy" must contain + "phy", "common". + + - vdda-phy-supply: Phandle to a regulator supply to PHY core block. + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. + +Optional properties: + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk + pll block. + +Required nodes: + - Each device node of QMP phy is required to have as many child nodes as + the number of lanes the PHY has. + +Required properties for child node: + - reg: list of offset and length pairs of register sets for PHY blocks - + tx, rx and pcs. + + - #phy-cells: must be 0 + + - clocks: a list of phandles and clock-specifier pairs, + one for each entry in clock-names. + - clock-names: Must contain following for pcie and usb qmp phys: + "pipe" for pipe clock specific to each lane. + + - resets: a list of phandles and reset controller specifier pairs, + one for each entry in reset-names. + - reset-names: Must contain following for pcie qmp phys: + "lane" for reset specific to each lane. + +Example: + phy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x034000 0x488>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + + pciephy_0: lane@0 { + reg = <0x035000 0x130>, + <0x035200 0x200>, + <0x035400 0x1dc>; + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "lane0"; + }; + + pciephy_1: lane@1 { + ... + ... + };