From patchwork Wed Feb 15 21:50:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 728400 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vNtH05p9kz9ryr for ; Thu, 16 Feb 2017 08:49:32 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752423AbdBOVtR (ORCPT ); Wed, 15 Feb 2017 16:49:17 -0500 Received: from mga09.intel.com ([134.134.136.24]:62932 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752287AbdBOVsX (ORCPT ); Wed, 15 Feb 2017 16:48:23 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Feb 2017 13:48:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,166,1484035200"; d="scan'208";a="45135072" Received: from tthayer-hp-z620-ubuntu.an.intel.com (HELO tthayer-HP-Z620-Ubuntu.altera.com) ([10.122.105.144]) by orsmga002.jf.intel.com with ESMTP; 15 Feb 2017 13:48:16 -0800 From: thor.thayer@linux.intel.com To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, linux@armlinux.org.uk, p.zabel@pengutronix.de Cc: thor.thayer@linux.intel.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/5] dt-bindings: mfd: Add Altera Arria10 SR Reset Controller bindings Date: Wed, 15 Feb 2017 15:50:12 -0600 Message-Id: <1487195416-23827-2-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1487195416-23827-1-git-send-email-thor.thayer@linux.intel.com> References: <1487195416-23827-1-git-send-email-thor.thayer@linux.intel.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thor Thayer This patch adds documentation for the Altera A10-SR Reset Controller DT bindings. Signed-off-by: Thor Thayer --- Documentation/devicetree/bindings/mfd/altera-a10sr.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt index ea151f2..c8a7365 100644 --- a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt @@ -18,6 +18,7 @@ The A10SR consists of these sub-devices: Device Description ------ ---------- a10sr_gpio GPIO Controller +a10sr_rst Reset Controller Arria10 GPIO Required Properties: @@ -27,6 +28,11 @@ Required Properties: the second cell is used to specify flags. See ../gpio/gpio.txt for more information. +Arria10 Peripheral PHY Reset +Required Properties: +- compatible : Should be "altr,a10sr-reset" +- #reset-cells : Should be one. + Example: resource-manager@0 { @@ -43,4 +49,9 @@ Example: gpio-controller; #gpio-cells = <2>; }; + + a10sr_rst: reset-controller { + compatible = "altr,a10sr-reset"; + #reset-cells = <1>; + }; };