From patchwork Tue Jan 17 08:00:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Reid X-Patchwork-Id: 716049 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3v2jG72WqGz9tkG for ; Tue, 17 Jan 2017 19:00:47 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751013AbdAQIAp (ORCPT ); Tue, 17 Jan 2017 03:00:45 -0500 Received: from anchovy3.45ru.net.au ([203.30.46.155]:55832 "EHLO anchovy.45ru.net.au" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750983AbdAQIAj (ORCPT ); Tue, 17 Jan 2017 03:00:39 -0500 Received: (qmail 18071 invoked by uid 5089); 17 Jan 2017 08:00:36 -0000 Received: by simscan 1.2.0 ppid: 18054, pid: 18056, t: 0.0280s scanners: regex: 1.2.0 attach: 1.2.0 clamav: 0.88.3/m:40/d:1950 Received: from unknown (HELO preid-centos7.electromag.com.au) (preid@electromag.com.au@203.59.230.133) by anchovy2.45ru.net.au with ESMTPA; 17 Jan 2017 08:00:36 -0000 Received: by preid-centos7.electromag.com.au (Postfix, from userid 1000) id 2EDF5302F68F0; Tue, 17 Jan 2017 16:00:33 +0800 (AWST) From: Phil Reid To: peda@axentia.se, wsa@the-dreams.de, robh+dt@kernel.org, mark.rutland@arm.com, preid@electromag.com.au, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 4/5] dt: bindings: i2c-mux-pca954x: Add documentation for nxp, irq-mask-enable Date: Tue, 17 Jan 2017 16:00:28 +0800 Message-Id: <1484640029-22870-5-git-send-email-preid@electromag.com.au> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1484640029-22870-1-git-send-email-preid@electromag.com.au> References: <1484640029-22870-1-git-send-email-preid@electromag.com.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Unfortunately some hardware device will assert their irq line immediately on power on and provide no mechanism to mask the irq. As the i2c muxes provide no method to mask irq line this provides a work around by keeping the parent irq masked until enough device drivers have loaded to service all pending interrupts. For example the the ltc1760 assert its SMBALERT irq immediately on power on. With two ltc1760 attached to bus 0 & 1 on a pca954x mux when the first device is registered irq are enabled and fire continuously as the second device driver has not yet loaded. Setting this parameter to <1 1> will delay the irq being enabled until both devices are ready. Signed-off-by: Phil Reid --- Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt index aa09704..ac71be6 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt @@ -19,6 +19,8 @@ Optional Properties: - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all children in idle state. This is necessary for example, if there are several multiplexers on the bus and the devices behind them use same I2C addresses. + - nxp,irq-mask-enable: array; Defines the minimum number of chips that must + register an irq for each channel before the parent irq line in enabled. - interrupt-parent: Phandle for the interrupt controller that services interrupts for this device. - interrupts: Interrupt mapping for IRQ. @@ -36,6 +38,7 @@ Example: #size-cells = <0>; reg = <0x74>; + nxp,irq-mask-enable = <0 0 0 0 1 0 0 0>; interrupt-parent = <&ipic>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; interrupt-controller;