From patchwork Thu Jan 5 09:25:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 711283 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tvMl23yvHz9t1L for ; Thu, 5 Jan 2017 20:26:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="F4gThheb"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031423AbdAEJ0V (ORCPT ); Thu, 5 Jan 2017 04:26:21 -0500 Received: from mail-wj0-f169.google.com ([209.85.210.169]:33867 "EHLO mail-wj0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936451AbdAEJ0E (ORCPT ); Thu, 5 Jan 2017 04:26:04 -0500 Received: by mail-wj0-f169.google.com with SMTP id tn15so30387379wjb.1 for ; Thu, 05 Jan 2017 01:26:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YR9Vb5HGJUjpifr3Uk6lzKwcbSkDrS+IMPspec3oD08=; b=F4gThhebylgEfGa0Gf7VSbakprtx44RFDERjzT8iTeCG7Qzoav5zL67V9rED4CWpVd q9BG5THjmbfFvbGfxO7gtAM9yXYQyLcG9XPgk6CzXlQ1MXj58UEqYDoK9BLNihPyDNRx tGW/qL+unUi6IeO/xKTW50MDQb3UHwl1xXELQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YR9Vb5HGJUjpifr3Uk6lzKwcbSkDrS+IMPspec3oD08=; b=oJqvKRICGGCvyKmdJrMO6/I25s42UH5hVNI0mfx3EM1lrSyS8sVlzEIxlnKEpy4SVf dFEiDKMETL5Z9yvXg4KX6DTviioi/ieAnpdErJ1KPRYdmdpvO1QSCGCE6xXtyz5yr1Ow ZS8fnSgkRBwKpAwizZrhdAa1WDif3Wpg4Q0kESiyDALVOcgE8ZUkXuCXjWfa+vqAVwwl 17r1PkSD6087dLD8Ri617ump8qSKIOemAggaEMMijbFLHrLP7wF4jFneC4twJ0/pHvjv Ks5ZQ7cuUtKhwt/KPOoXaTgwC9n1pgAEvhYJjNIeoSUDYTzwudtdZConLrn2cbD4PmjQ B2pQ== X-Gm-Message-State: AIkVDXIDl0XY/5Hh0eP+M0NYD8kROnNI7QeHs0m4d2wImPfVtb/z/DhLPa9MJKGr9caHxanv X-Received: by 10.194.141.98 with SMTP id rn2mr60301064wjb.1.1483608362579; Thu, 05 Jan 2017 01:26:02 -0800 (PST) Received: from lmenx321.st.com. ([80.215.39.25]) by smtp.gmail.com with ESMTPSA id w18sm99401549wme.9.2017.01.05.01.26.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 05 Jan 2017 01:26:02 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v7 3/8] PWM: add pwm-stm32 DT bindings Date: Thu, 5 Jan 2017 10:25:39 +0100 Message-Id: <1483608344-9012-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483608344-9012-1-git-send-email-benjamin.gaignard@st.com> References: <1483608344-9012-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for pwm-stm32 version 6: - change st,breakinput parameter format to make it usuable on stm32f7 too. version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard Acked-by: Rob Herring --- .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..866f222 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,33 @@ +STMicroelectronics STM32 Timers PWM bindings + +Must be a sub-node of an STM32 Timers device tree node. +See ../mfd/stm32-timers.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt + +Optional parameters: +- st,breakinput: Arrays of three u32 to describe break input configurations. + "index" indicates on which break input the configuration should be applied. + "level" gives the active level (0=low or 1=high) for this configuration. + "filter" gives the filtering value to be applied. + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + st,breakinput = <0 1 5>; + }; + };