From patchwork Thu Jan 5 09:25:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 711282 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tvMk96n1Kz9t2D for ; Thu, 5 Jan 2017 20:26:09 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="X3HijFkV"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762105AbdAEJ0H (ORCPT ); Thu, 5 Jan 2017 04:26:07 -0500 Received: from mail-wj0-f179.google.com ([209.85.210.179]:33823 "EHLO mail-wj0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760543AbdAEJZ6 (ORCPT ); Thu, 5 Jan 2017 04:25:58 -0500 Received: by mail-wj0-f179.google.com with SMTP id tn15so30385586wjb.1 for ; Thu, 05 Jan 2017 01:25:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Dm56TOezN4As/Mt9cTpUOd4KL6Igo1uwMcz3TEXRIH4=; b=X3HijFkVQoU2WxI3tpRpd3ItEKcASd1YzVP8+UWp/46vqLiLq+MhTl24fz15lmqJhq KYLPIe7gMpH8u4yaUgvudtVwemlQ80IrvnUtjX9I3pGhvkCus8XtFVBGklX9/th6DoeA vO+4ccOEXiVd0oTlRwddGn35AfISAQZ7tgtkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Dm56TOezN4As/Mt9cTpUOd4KL6Igo1uwMcz3TEXRIH4=; b=LiEQwVsx3YTqkTq+o1LKu/7WgAZx43bJtT4Aqg7o25mvDp4G9gTbCgNQ4NdjnpD9ni /SGZwn1MCzCtul2I7p1qek7RU1YkpozYVfwaMvmtOhfdnFIxrx8xEIKWi9zSTUXpIS9i FvFCcQqIOAIa6Z+sWkjgKuipmTq6r48ju+0+QxqyC0a9Epu+vUSMR/BVlrX0454vWWps NxSQe/o7U4oC3K2kLSI1X1OYKPCnPSq5xunhC4sBswMN5H9isXrSmI2W/fUT8Db6GEGx Uwqlhxhk+rv0/B/jPAGukzVhMkmpIc6LRW79qbLHduqW/mDUpFi7yUals3wgjWkn9MMC tocw== X-Gm-Message-State: AIkVDXLWT+NFBn0+W5wrQU8yIIZoI5hYwJEzICBXfIFoixY6Aiv3+cak2Kn3vsODkENeXvIm X-Received: by 10.194.44.74 with SMTP id c10mr687486wjm.72.1483608357089; Thu, 05 Jan 2017 01:25:57 -0800 (PST) Received: from lmenx321.st.com. ([80.215.39.25]) by smtp.gmail.com with ESMTPSA id w18sm99401549wme.9.2017.01.05.01.25.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 05 Jan 2017 01:25:56 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v7 1/8] MFD: add bindings for STM32 Timers driver Date: Thu, 5 Jan 2017 10:25:37 +0100 Message-Id: <1483608344-9012-2-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1483608344-9012-1-git-send-email-benjamin.gaignard@st.com> References: <1483608344-9012-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings information for STM32 Timers version 6: - rename stm32-gtimer to stm32-timers - change compatible - add description about the IPs version 2: - rename stm32-mfd-timer to stm32-gptimer - only keep one compatible string Signed-off-by: Benjamin Gaignard Acked-by: Rob Herring --- .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt new file mode 100644 index 0000000..a73301d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -0,0 +1,46 @@ +STM32 Timers driver bindings + +This IP provides 3 types of timer along with PWM functionality: +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels. +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a + programmable prescaler and PWM outputs. +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. + +Required parameters: +- compatible: must be "st,stm32-timers" + +- reg: Physical base address and length of the controller's + registers. +- clock-names: Set to "int". +- clocks: Phandle to the clock used by the timer module. + For Clk properties, please refer to ../clock/clock-bindings.txt + +Optional parameters: +- resets: Phandle to the parent reset controller. + See ../reset/st,stm32-rcc.txt + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32.txt +- timer: See ../iio/timer/stm32-timer-trigger.txt + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + + timer { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + }; + };