From patchwork Fri Dec 9 14:15:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 704581 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tZvTj6HPlz9s2G for ; Sat, 10 Dec 2016 01:18:17 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Ie1fuS8n"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753944AbcLIOQX (ORCPT ); Fri, 9 Dec 2016 09:16:23 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:32897 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932752AbcLIOQV (ORCPT ); Fri, 9 Dec 2016 09:16:21 -0500 Received: by mail-wm0-f43.google.com with SMTP id c184so13767297wmd.0 for ; Fri, 09 Dec 2016 06:16:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TnWfGaT6tnzhMwUYsSuKIwDlHI5ukKRfRMl+HNxHi7I=; b=Ie1fuS8nA6BwxTstU5aKu2vb9VDVhO2U2pT5/dt6xnrxhaC143mQvX2Ig7dWdPUFLM y74fFL7HoOriE/x84xEisTEu71vSk53juSa5Wtq2L/vv6ayE3jp5PE6W4mSKXi4gqX9W +fP6Q80Ylo7Oj9KNVlVB+9bgLrtfMCsSAfjPE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TnWfGaT6tnzhMwUYsSuKIwDlHI5ukKRfRMl+HNxHi7I=; b=gYJMTQUJW6TSy40AS0pv3eS+w8QOAOGGyYvMtH8a/MLpGGpdqn7N6mEj5kyB+xfhFR emogC1yfx3yvsOS8n9z7NixnhT9e6O6eH7una7gUM+iOqaZKBiWHIF2wStHn64xH01C7 ljzAqvXkVv9rtydfKnz+7+/GnKS59IRS20yrWjKAdG2A5NBaLwb4cdz+yHzj0rmGQlHu De5ggJMGr3xsNzJcCKNT4uwuYtZJtaxDet1Rq+jeFfew+8gN/Pk+LA8hPLR34qVwHVZW tOJdat6wLiZKUPhGBe2nPmPg7Nig0ul421z8GdGsxx6UkalFoxrnGURHdQCdDbUHksp7 hBLg== X-Gm-Message-State: AKaTC02m69xnN2jQ6PQllsM7Auq0+WBsmIQp+5rMEULr8NQiODzKPFLza72d2+/QxVWamZfE X-Received: by 10.28.234.85 with SMTP id i82mr6712461wmh.6.1481292979214; Fri, 09 Dec 2016 06:16:19 -0800 (PST) Received: from lmenx321.st.com. ([80.215.96.58]) by smtp.gmail.com with ESMTPSA id j6sm42589344wjk.25.2016.12.09.06.16.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Dec 2016 06:16:18 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v6 1/8] MFD: add bindings for STM32 Timers driver Date: Fri, 9 Dec 2016 15:15:12 +0100 Message-Id: <1481292919-26587-2-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481292919-26587-1-git-send-email-benjamin.gaignard@st.com> References: <1481292919-26587-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings information for STM32 Timers version 6: - rename stm32-gtimer to stm32-timers - change compatible - add description about the IPs version 2: - rename stm32-mfd-timer to stm32-gptimer - only keep one compatible string Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/mfd/stm32-timers.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt new file mode 100644 index 0000000..b30868e --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt @@ -0,0 +1,46 @@ +STM32 Timers driver bindings + +This IP provides 3 types of timer along with PWM functionality: +- advanced-control timers consist of a 16-bit auto-reload counter driven by a programmable + prescaler, break input feature, PWM outputs and complementary PWM ouputs channels. +- general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a + programmable prescaler and PWM outputs. +- basic timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. + +Required parameters: +- compatible: must be "st,stm32-timers" + +- reg: Physical base address and length of the controller's + registers. +- clock-names: Set to "clk_int". +- clocks: Phandle to the clock used by the timer module. + For Clk properties, please refer to ../clock/clock-bindings.txt + +Optional parameters: +- resets: Phandle to the parent reset controller. + See ../reset/st,stm32-rcc.txt + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32.txt +- timer: See ../iio/timer/stm32-timer-trigger.txt + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + + timer { + compatible = "st,stm32-timer-trigger"; + reg = <0>; + }; + };