From patchwork Thu Dec 8 12:20:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 704046 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tZF91003Wz9sCM for ; Thu, 8 Dec 2016 23:31:32 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="iQFlU1eY"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753280AbcLHMbX (ORCPT ); Thu, 8 Dec 2016 07:31:23 -0500 Received: from mail-wm0-f43.google.com ([74.125.82.43]:37445 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932453AbcLHMbW (ORCPT ); Thu, 8 Dec 2016 07:31:22 -0500 Received: by mail-wm0-f43.google.com with SMTP id t79so23176155wmt.0 for ; Thu, 08 Dec 2016 04:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nyuQucMrxSHUeiOy0wKji+6F0ZoqGW8/l9vPeyyeykk=; b=iQFlU1eYct5U7fLVBGrP+4U02b+na+CEaR2SW4g9T/irZbHNRef29l1mFuR0fUbAzE Qcp6w7Df1HzlxsES0OyiFAjwwOkQAmjXCZqD035k16WYhQevfnSm/xEXR9YNd3QvWki5 3rlookFIND9pYR/XBoldsqV0mzZgGyFSCdEr4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nyuQucMrxSHUeiOy0wKji+6F0ZoqGW8/l9vPeyyeykk=; b=ArvaBwqYMzX4nvkmjP/9816EOkLjvMRPZS65Kmq0k11eGYzi3N9UWHvgQ3ucDfEf/2 9q+25s+A5iguydknxi5HZOgNjHvOLzN8v8uYCbsWBltRGcou9c1Rv4fIhTzVh8HoVmX1 UXPSBQP0ZjvaWQLJh8xDoWgQdvj2YXSUuXY4LAvKlTe1cOsiOtBY8lLOz/o9VhkdaquX aLDfjhCTkFHJ2QVQdaUzO5aU8YugFCqYfBI/1ddpqWjhQqPBORpwofLv4dgoihkC8bsl 0mZyXu1etFq9dJY4LgWsxfKqld3tbiEssbc1zA///4vkd1bsR8M3YSAIKdD2i/UZPkUp GWpA== X-Gm-Message-State: AKaTC02+EszS3P7bRKWHdsncAeltcD2Ijobwkbu5e6iuAM2RW+rYmsAPmspF4nLVILlFPVif X-Received: by 10.28.26.197 with SMTP id a188mr1853870wma.93.1481199724120; Thu, 08 Dec 2016 04:22:04 -0800 (PST) Received: from lmenx321.st.com. ([80.214.68.50]) by smtp.gmail.com with ESMTPSA id f10sm36718072wjl.28.2016.12.08.04.22.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Dec 2016 04:22:03 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v5 3/7] PWM: add pwm-stm32 DT bindings Date: Thu, 8 Dec 2016 13:20:46 +0100 Message-Id: <1481199650-22484-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481199650-22484-1-git-send-email-benjamin.gaignard@st.com> References: <1481199650-22484-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for pwm-stm32 version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..b8ea660 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,33 @@ +STMicroelectronics STM32 General Purpose Timer PWM bindings + +Must be a sub-node of an STM32 General Purpose Timer device tree node. +See ../mfd/stm32-general-purpose-timer.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt + +Optional parameters: +- st,breakinput-polarity: If present, a break input is available + for the channel. In that case the property value denotes the + polarity of the break input: + - 0: active low + - 1: active high + +Example: + timers@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm@0 { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + };