From patchwork Tue Dec 6 12:38:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 703131 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tY1Zg5cFNz9vMb for ; Tue, 6 Dec 2016 23:46:03 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="H8S5z4EX"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752102AbcLFMpu (ORCPT ); Tue, 6 Dec 2016 07:45:50 -0500 Received: from mail-wm0-f52.google.com ([74.125.82.52]:36047 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752330AbcLFMkJ (ORCPT ); Tue, 6 Dec 2016 07:40:09 -0500 Received: by mail-wm0-f52.google.com with SMTP id g23so127134244wme.1 for ; Tue, 06 Dec 2016 04:39:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3bOj5imuSk5hc0cFXKU7BkDLVjkCryA54ewR0T+lhjk=; b=H8S5z4EXp35xpa55xZzVDHlLl7Cu+IAottwqe+qbr/r13sXdi5bBrfmcXIAfHNB4gE 5sdUcYSQRP1+vIb/xl4Ln5U4Cs/mG++UkwXV9h408HLPsgqLZvPOwRTCiICpTU3NfYtU T7BMXGeGfu+zILR1bMlpR/ViTKlNker/afnNI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3bOj5imuSk5hc0cFXKU7BkDLVjkCryA54ewR0T+lhjk=; b=YQSR5JpdREnt+tMttezJWs2EEfLtYA8QsvqFx/Z7urcOTB6PLKwp19UvWDoNT6hf+1 FmtX4qajfX5b9VrtcG1UQBASi7wzqduGBKj41dCKYdAo4tvf8dtohGz9CTx0lrGIATUh fC+f9Lv0lYa4doRGHXOalbjQscajwvSgBeB6Cb1FHuE/Jwt7gsxVsmlfbbjp+BI5obpc SdQVSrteKqyX1e8d8IBQvpoMSNs5HNCKL9z4u5NKUSGMFm5U7V9lIem8rpOf1wp1rq8D PVzVUtpRufpwwyz/jDemy0BY98YyL5gNp6yljDx1FQxSNWryh8/ORzsdgty6TfInGMbi 8l1A== X-Gm-Message-State: AKaTC01PLTOk8YhJWT7Tn+8+akfvRveHXND1sdAsjYv//UAnG9ZPzGymDVc2atRN8tXHkCye X-Received: by 10.28.145.66 with SMTP id t63mr2387679wmd.99.1481027991247; Tue, 06 Dec 2016 04:39:51 -0800 (PST) Received: from lmenx321.st.com. ([80.215.93.98]) by smtp.gmail.com with ESMTPSA id k2sm25598089wjv.11.2016.12.06.04.39.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Dec 2016 04:39:50 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v4 3/7] PWM: add pwm-stm32 DT bindings Date: Tue, 6 Dec 2016 13:38:45 +0100 Message-Id: <1481027929-13704-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481027929-13704-1-git-send-email-benjamin.gaignard@st.com> References: <1481027929-13704-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for pwm-stm32 version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..c0cc246 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,33 @@ +STMicroelectronics STM32 General Purpose Timer PWM bindings + +Must be a sub-node of an STM32 General Purpose Timer device tree node. +See ../mfd/stm32-general-purpose-timer.txt for details about the parent node. + +Required parameters: +- compatible: Must be "st,stm32-pwm". +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes for PWM module. + For Pinctrl properties see ../pinctrl/pinctrl-bindings.txt + +Optional parameters: +- st,breakinput-polarity: If present, a break input is available + for the channel. In that case the property value denotes the + polarity of the break input: + - 0: active low + - 1: active high + +Example: + gptimer@40010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm@0 { + compatible = "st,stm32-pwm"; + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + }; + };