From patchwork Fri Dec 2 10:17:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 701893 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tVVWB08pLz9vFl for ; Fri, 2 Dec 2016 21:19:18 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="WQdLuKy9"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759577AbcLBKRy (ORCPT ); Fri, 2 Dec 2016 05:17:54 -0500 Received: from mail-wm0-f54.google.com ([74.125.82.54]:35619 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759539AbcLBKRp (ORCPT ); Fri, 2 Dec 2016 05:17:45 -0500 Received: by mail-wm0-f54.google.com with SMTP id a197so12152477wmd.0 for ; Fri, 02 Dec 2016 02:17:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Lf86NiIrUt4UqV6rUCF7iz/WqrCCsNK4HC7y96t8Jtk=; b=WQdLuKy9NYyaaiopNGMKaW9mV7GznTBnfbS7VjJ4z9dKYhrDjVpJgyVgwGferC1QmX dd6JfYI/mGqkzUczI1VcNEwlomKL/KQYEZmRddkXMVy0+EFGAHbLqwuJDakMwNGG09iL ixoUod5hZGb2KTQqPvY7sj/wMTYttOztqaAP0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Lf86NiIrUt4UqV6rUCF7iz/WqrCCsNK4HC7y96t8Jtk=; b=KVP0LMS9X93jgjpyBokmrwgSc3JNlEZIXPyWURCgsETOZ5qhJRJa+sc4Z0VC/QI1MM OAuF6NE+0orpvF2NBxdgsutqeW051Y5Njl9btEcGJO+y+nuqG8SWNbFOhcRijTsIcxKx brAd7ScMmWl0s4VAmMPnVvPmumt+6/Y/hQ4ddkfOPwesLoKx5Q3tq/DrGDOA4AfeDNSg fRaAmncnHLN6OTqyNTwFotc20+zYpMe4sF7KgwRKjv1a/rD3q1m+u36D/8HwYcThan/j u0IHLYyELxLdfufQ4zYwKQPC3PfPDDioGmCx+7koAi8uMrERbfHul3ZK7QXRdA3gtz9O /MaQ== X-Gm-Message-State: AKaTC01oaLOawwVsSDKn7TGslDPfHuHNEj7ekZt3U2c2zTLMiLpgDmrWCtUSOkia2e7phR0B X-Received: by 10.28.152.79 with SMTP id a76mr2227588wme.47.1480673864202; Fri, 02 Dec 2016 02:17:44 -0800 (PST) Received: from lmenx321.st.com. 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[88.175.155.153]) by smtp.gmail.com with ESMTPSA id c133sm2422503wme.12.2016.12.02.02.17.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Dec 2016 02:17:43 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings Date: Fri, 2 Dec 2016 11:17:18 +0100 Message-Id: <1480673842-20804-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480673842-20804-1-git-send-email-benjamin.gaignard@st.com> References: <1480673842-20804-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for pwm-stm32 version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/pwm/pwm-stm32.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..575b9fb --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,38 @@ +STMicroelectronics PWM driver bindings for STM32 + +Must be a sub-node of STM32 general purpose timer driver +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt + +Required parameters: +- compatible: Must be "st,stm32-pwm" +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes + for PWM module. + For Pinctrl properties, please refer to [1]. + +Optional parameters: +- st,breakinput: Set if the hardware have break input capabilities +- st,breakinput-polarity: Set break input polarity. Default is 0 + The value define the active polarity: + - 0 (active LOW) + - 1 (active HIGH) +- st,pwm-num-chan: Number of available PWM channels. Default is 0. +- st,32bits-counter: Set if the hardware have a 32 bits counter +- st,complementary: Set if the hardware have complementary output channels + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + gptimer1: gptimer1@40010000 { + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm1@0 { + compatible = "st,stm32-pwm"; + st,pwm-num-chan = <4>; + st,breakinput; + st,complementary; + }; + };