From patchwork Fri Dec 2 10:17:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 701897 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tVVX23NF8z9vGS for ; Fri, 2 Dec 2016 21:20:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RYPBuKGj"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932799AbcLBKTr (ORCPT ); Fri, 2 Dec 2016 05:19:47 -0500 Received: from mail-wj0-f169.google.com ([209.85.210.169]:35339 "EHLO mail-wj0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759432AbcLBKRm (ORCPT ); Fri, 2 Dec 2016 05:17:42 -0500 Received: by mail-wj0-f169.google.com with SMTP id v7so227678850wjy.2 for ; Fri, 02 Dec 2016 02:17:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qe3DQuPBCHl8zwQPA1J+eN2Ja1DJDBiuKuxl9WGahBs=; b=RYPBuKGjhRuyaEwHjLCqgn6ca68wke6lmJxPouFsejH/1lUWnkZIOHOaF1hX7hUT2B JhUE2CYXJvW3ooNCZCDQqbDKMO0i93KrSS+YogRx5A0h/JzFnybY16NDOEYtuLtUv+v4 GIlVbHj3AVyfv5pWbEwDudtRuqPRB5eEUdB9g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qe3DQuPBCHl8zwQPA1J+eN2Ja1DJDBiuKuxl9WGahBs=; b=IuecglICRNh9JLpVrI4e+NcT7Sn0FlihgboVavH/A45sAWOR0f7S21rSkNrRG1YA6Y sx/Jf9XetPRqL1vhDvSYfe4vfHtPMaz4eRFyGj/v/OSryiW4+DQOlywCoJzRWIb0x332 JvI+cwA17w5gy4yrIUb72rhYMpCIVnBrWinxPEepgnYSHXnJf7HDrmKnVoqniX2hRlwd DHIx7uZ72NS+fe4TiaVMx2P720IsCDrlx8I8MnW916lgel+S4UqgJ0B6vgvtpdCf/Gyu UAMnuMlnOWWDXypfrOBIkgdOFLTvFdcn0viBIXl69Q5Y2OfEMJtuK/LzxWXp8UDMZM9U 6ZSg== X-Gm-Message-State: AKaTC00coWOUUiSA0Tu0V3DOJ56IiWZrxjAS0tXzCjmdaUOYA83CaPCQZ78F28xljOvlYy62 X-Received: by 10.194.66.101 with SMTP id e5mr36610451wjt.172.1480673860345; Fri, 02 Dec 2016 02:17:40 -0800 (PST) Received: from lmenx321.st.com. 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[88.175.155.153]) by smtp.gmail.com with ESMTPSA id c133sm2422503wme.12.2016.12.02.02.17.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Dec 2016 02:17:39 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v3 1/7] MFD: add bindings for stm32 general purpose timer driver Date: Fri, 2 Dec 2016 11:17:16 +0100 Message-Id: <1480673842-20804-2-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480673842-20804-1-git-send-email-benjamin.gaignard@st.com> References: <1480673842-20804-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings information for stm32 general purpose timer version 2: - rename stm32-mfd-timer to stm32-gptimer - only keep one compatible string Signed-off-by: Benjamin Gaignard --- .../bindings/mfd/stm32-general-purpose-timer.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt new file mode 100644 index 0000000..4fc55d1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt @@ -0,0 +1,47 @@ +STM32 general purpose timer driver + +Required parameters: +- compatible: must be "st,stm32-gptimer" + +- reg: Physical base address and length of the controller's + registers. +- clock-names: Set to "clk_int". +- clocks: Phandle to the clock used by the timer module. + For Clk properties, please refer to ../clock/clock-bindings.txt + +Optional parameters: +- resets: Phandle to the parent reset controller. + See ../reset/st,stm32-rcc.txt + +Optional subnodes: +- pwm: See ../pwm/pwm-stm32.txt +- timer: See ../iio/timer/stm32-timer-trigger.txt + +Example: + gptimer1: gptimer1@40010000 { + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm1@0 { + compatible = "st,stm32-pwm"; + st,pwm-num-chan = <4>; + st,breakinput; + st,complementary; + }; + + timer1@0 { + compatible = "st,stm32-timer-trigger"; + interrupts = <27>; + st,input-triggers-names = TIM5_TRGO, + TIM2_TRGO, + TIM4_TRGO, + TIM3_TRGO; + st,output-triggers-names = TIM1_TRGO, + TIM1_CH1, + TIM1_CH2, + TIM1_CH3, + TIM1_CH4; + }; + };