From patchwork Thu Nov 24 15:14:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 698903 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tPjW61G9wz9t2G for ; Fri, 25 Nov 2016 02:17:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="Kb+LvwIE"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965860AbcKXPRe (ORCPT ); Thu, 24 Nov 2016 10:17:34 -0500 Received: from mail-wj0-f181.google.com ([209.85.210.181]:36262 "EHLO mail-wj0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966091AbcKXPPh (ORCPT ); Thu, 24 Nov 2016 10:15:37 -0500 Received: by mail-wj0-f181.google.com with SMTP id qp4so35794052wjc.3 for ; Thu, 24 Nov 2016 07:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aD2PkbOZNY1r3x6esy6giNr0sJSvfKqNJY366DLPsdY=; b=Kb+LvwIENOYe9YtvnYTcoQrAH3La07ZybS8mjbP1hYESwUHyLJfEKfsn90n4LF92u+ TmPdQh6z6ucMCxVbBdH5WeLyo2BFPq2ZavWYXp8yRCEX5hZr0li+5C/6oCQqMazNopEg U3Tzh/jSYR/Zmkt+Zo9HmbjDlUKfSoNWArK3M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aD2PkbOZNY1r3x6esy6giNr0sJSvfKqNJY366DLPsdY=; b=E2WTjKZUgY9IXJfjE/DrTfhxo9g7g3oHDGs94NePM7LiPROTZJ5lhkwnu0Bap7zRV/ FVQAk0zbNoAM2+1cSrNZooaYrHdlzAEimp3igz6Rt4/b4y31SzoT6or6U7Ice9ZZMDvT Zfn8KlZwsQXEZtJ54jiwCkwFShh1u0FDRHG///42ae1/0XanhxQkGZZ81XolRAc/K4sL MR3SXopLyVV1fL+dwb11F0Ncx53W9a4xrazj9vTy7Ebb7LaqMm7x/xt4cF0ADOBBFvY5 3SE5saqAsa3z3Nx1wf8v7414YauI/VWOU8wCISLS1Cla3zs2Bo/zGgmhFUJ0dca/tR8h 6GcQ== X-Gm-Message-State: AKaTC018eRL4gVRTWrW+YJOLaevHwuT7QkydFsucvuZrA2098rrifNO/jl5/Vzf2dRG7r3nn X-Received: by 10.194.109.65 with SMTP id hq1mr2731334wjb.37.1480000490086; Thu, 24 Nov 2016 07:14:50 -0800 (PST) Received: from lmenx321.st.com. ([80.215.203.217]) by smtp.gmail.com with ESMTPSA id ct7sm24062084wjc.2.2016.11.24.07.14.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 24 Nov 2016 07:14:49 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, benjamin.gaignard@linaro.org, Benjamin Gaignard Subject: [PATCH v2 3/7] PWM: add pwm-stm32 DT bindings Date: Thu, 24 Nov 2016 16:14:19 +0100 Message-Id: <1480000463-9625-4-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> References: <1480000463-9625-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define bindings for pwm-stm32 version 2: - use parameters instead of compatible of handle the hardware configuration Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/pwm/pwm-stm32.txt | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt new file mode 100644 index 0000000..36263f0 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt @@ -0,0 +1,37 @@ +STMicroelectronics PWM driver bindings for STM32 + +Must be a sub-node of STM32 general purpose timer driver + +Required parameters: +- compatible: Must be "st,stm32-pwm" +- pinctrl-names: Set to "default". +- pinctrl-0: List of phandles pointing to pin configuration nodes + for PWM module. + For Pinctrl properties, please refer to [1]. + +Optional parameters: +- st,breakinput: Set if the hardware have break input capabilities +- st,breakinput-polarity: Set break input polarity. Default is 0 + The value define the active polarity: + - 0 (active LOW) + - 1 (active HIGH) +- st,pwm-num-chan: Number of available PWM channels. Default is 0. +- st,32bits-counter: Set if the hardware have a 32 bits counter +- st,complementary: Set if the hardware have complementary output channels + +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + gptimer1: gptimer1@40010000 { + compatible = "st,stm32-gptimer"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "clk_int"; + + pwm1@0 { + compatible = "st,stm32-pwm"; + st,pwm-num-chan = <4>; + st,breakinput; + st,complementary; + }; + };