From patchwork Tue Nov 22 16:13:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 697780 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tNW1B5Ptrz9t0G for ; Wed, 23 Nov 2016 03:21:02 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="UvbqaQEU"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755443AbcKVQVC (ORCPT ); Tue, 22 Nov 2016 11:21:02 -0500 Received: from mail-wj0-f182.google.com ([209.85.210.182]:34078 "EHLO mail-wj0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753804AbcKVQVB (ORCPT ); Tue, 22 Nov 2016 11:21:01 -0500 X-Greylist: delayed 428 seconds by postgrey-1.27 at vger.kernel.org; Tue, 22 Nov 2016 11:21:01 EST Received: by mail-wj0-f182.google.com with SMTP id mp19so44771828wjc.1 for ; Tue, 22 Nov 2016 08:21:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rrvCzch+ong/sh1s+mn3PxeZoo2SngKnozdQu19wJ8o=; b=UvbqaQEUnz9J8sf+8lYmrBGne4iPnRz0VAfpDX3ZgeZQulj1/z0P84Uf0Os/3AlW5J SOJTXALNsAFZZDI7Xii12A+bkLJzkLZ/4lYSytRlFJHGvLysn1o3WzjHwrqnXDuDOU3v TYUzOVHevlvZ6FgOLUmZ0KihZnCBwinxS/Cqk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rrvCzch+ong/sh1s+mn3PxeZoo2SngKnozdQu19wJ8o=; b=jJLDQF99MZstTtWK6ir455Cn6QXUECNHTGAQWPKn1I54zOkBoQ3HDTIzHP2KePsyXH PX5/aBL8QL3ms6QLvgv/UC9wiwr3Z8k5KD+idHPqwnkR++Db+iDIFhMUGIkaaf/J1JPr T6Esfa3epSb+46zOlRhZCQ6r9Nlg+PG+9RECtWXF4I3WgQrUJUCIU6Kn1lSyroFe83RN Sf/V4z5YuCbpvGWIipHQULt5ojV08kuF8uYQH5tM+ha8Nc6zyzRYGPQlnmJJR2Nedaix Vo83e9/00fJvAhi/qGV4+KVRgwcKLoMAzUih35IvdiOWMY+NLbSinJ+yb9BsTWDvVsfG G6Fw== X-Gm-Message-State: AKaTC00a138KlLxZXxVigGIVKZqZJR/HIesr0UUnHUG51KZb7x38B2jRVwm28owL/VeyhS3n X-Received: by 10.195.11.229 with SMTP id el5mr18127841wjd.64.1479831232618; Tue, 22 Nov 2016 08:13:52 -0800 (PST) Received: from lmenx321.st.com. ([80.215.80.240]) by smtp.gmail.com with ESMTPSA id v202sm3729369wmv.8.2016.11.22.08.13.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Nov 2016 08:13:52 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, linux-pwm@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, linux-iio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: fabrice.gasnier@st.com, gerald.baeza@st.com, arnaud.pouliquen@st.com, linus.walleij@linaro.org, linaro-kernel@lists.linaro.org, Benjamin Gaignard Subject: [PATCH 1/7] add binding for stm32 multifunctions timer driver Date: Tue, 22 Nov 2016 17:13:21 +0100 Message-Id: <1479831207-32699-2-git-send-email-benjamin.gaignard@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com> References: <1479831207-32699-1-git-send-email-benjamin.gaignard@st.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add bindings information for stm32 timer MFD Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/mfd/stm32-timer.txt | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt diff --git a/Documentation/devicetree/bindings/mfd/stm32-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-timer.txt new file mode 100644 index 0000000..3cefce1 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/stm32-timer.txt @@ -0,0 +1,53 @@ +STM32 multifunctions timer driver + +stm32 timer MFD allow to handle at the same time pwm and IIO timer devices + +Required parameters: +- compatible: must be one of the follow value: + "st,stm32-mfd-timer1" + "st,stm32-mfd-timer2" + "st,stm32-mfd-timer3" + "st,stm32-mfd-timer4" + "st,stm32-mfd-timer5" + "st,stm32-mfd-timer6" + "st,stm32-mfd-timer7" + "st,stm32-mfd-timer8" + "st,stm32-mfd-timer9" + "st,stm32-mfd-timer10" + "st,stm32-mfd-timer11" + "st,stm32-mfd-timer12" + "st,stm32-mfd-timer13" + "st,stm32-mfd-timer14" + +- reg : Physical base address and length of the controller's + registers. +- clock-names: Set to "mfd_timer_clk". +- clocks: Phandle of the clock used by the timer module. + For Clk properties, please refer to [1]. +- interrupts : Reference to the timer interrupt + +Optional parameters: +- resets : Reference to a reset controller asserting the timer + +Optional subnodes: +- pwm: See Documentation/devicetree/bindings/pwm/pwm-stm32.txt +- iiotimer: See Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Example: + mfd_timer1: mfdtimer1@40010000 { + compatible = "st,stm32-mfd-timer1"; + reg = <0x40010000 0x400>; + clocks = <&rcc 0 160>; + clock-names = "mfd_timer_clk"; + interrupts = <27>; + + pwm1: pwm1@40010000 { + compatible = "st,stm32-pwm1"; + }; + + iiotimer1: iiotimer1@40010000 { + compatible = "st,stm32-iio-timer1"; + }; + };