From patchwork Tue Nov 22 12:02:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 697664 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3tNPJb1ZfPz9sXx for ; Tue, 22 Nov 2016 23:03:59 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="ZR4QaNY/"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="Ft4jY/Lm"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755412AbcKVMDE (ORCPT ); Tue, 22 Nov 2016 07:03:04 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:47174 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755408AbcKVMDC (ORCPT ); Tue, 22 Nov 2016 07:03:02 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8F6EF61503; Tue, 22 Nov 2016 12:03:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479816181; bh=7JCIvM2MADyweP7xQqgybubx9lxVjWOSff4TVS2vKcI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZR4QaNY/ygVM633QYRhksKg//JnsMUuuusWr7yOp0ZXlTLU968vne5HjPqdGs+sSD wT7PO/X31KTs2/WwiKmNUPcnDx/fPsGWFtT0V/hKFngBCuo1OHU1fxI0KrXmaxoq03 fEeefehPog+7eyRA+7kfkXgSO442uO8iewSB2Rds= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,SPF_PASS,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from blr-ubuntu-41.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AEDCB61503; Tue, 22 Nov 2016 12:02:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1479816180; bh=7JCIvM2MADyweP7xQqgybubx9lxVjWOSff4TVS2vKcI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ft4jY/LmXv4sbicg+5UVYwpqGfZTaQgv4gO8/eyDqXaeqV1kijKSyNUKgNZppIKsF SxblitB2Y+bHttpCe+yitRyEhO5fucpD7bYzmmoZPi0mAHU0NEHiFO46+ZREDdktBH G2LEleY8Fcqj8JJ1PwIu0g0E4DcnMVAMaC/Spi3k= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org AEDCB61503 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: kishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: srinivas.kandagatla@linaro.org, sboyd@codeaurora.org, linux-arm-msm@vger.kernel.org, Vivek Gautam Subject: [PATCH v2 1/4] dt-bindings: phy: Add support for QUSB2 phy Date: Tue, 22 Nov 2016 17:32:40 +0530 Message-Id: <1479816163-5260-2-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> References: <1479816163-5260-1-git-send-email-vivek.gautam@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm chipsets have QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller. Adding dt binding information for the same. Signed-off-by: Vivek Gautam --- Changes since v1: - New patch, forked out of the original driver patch: "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips" - Updated dt bindings to remove 'hstx-trim-bit-offset' and 'hstx-trim-bit-len' bindings. .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt new file mode 100644 index 0000000..38c8b30 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt @@ -0,0 +1,55 @@ +Qualcomm QUSB2 phy controller +============================= + +QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. + +Required properties: + - compatible: compatible list, contains "qcom,msm8996-qusb2-phy". + - reg: offset and length of the PHY register set. + - #phy-cells: must be 0. + + - clocks: a list of phandles and clock-specifier pairs, + one for each entry in clock-names. + - clock-names: must be "cfg_ahb" for phy config clock, + "ref_clk" for 19.2 MHz ref clk, + "ref_clk_src" reference clock source. + "iface" for phy interface clock (Optional). + + - vdd-phy-supply: Phandle to a regulator supply to PHY core block. + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. + - vdda-phy-dpdm: Phandle to 3.1V regulator supply to Dp/Dm port signals. + + - resets: a list of phandles and reset controller specifier pairs, + one for each entry in reset-names. + - reset-names: must be "phy" for reset of phy block. + +Optional properties: + - nvmem-cells: a list of phandles to nvmem cells that contain fused + tuning parameters for qusb2 phy, one for each entry + in nvmem-cell-names. + - nvmem-cell-names: must be "tune2_hstx_trim_efuse" for cell containing + HS Tx trim value. + + - qcom,tcsr-syscon: Phandle to TCSR syscon register region. + +Example: + hsphy: qusb2phy@7411000 { + compatible = "qcom,msm8996-qusb2-phy"; + reg = <0x07411000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>, + <&rpmcc MSM8996_RPM_SMD_LN_BB_CLK>; + clock-names = "cfg_ahb_clk", "ref_clk", "ref_clk_src"; + + vdd-phy-supply = <&pm8994_s2>; + vdda-pll-supply = <&pm8994_l12>; + vdda-phy-dpdm-supply = <&pm8994_l24>; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy"; + + nvmem-cells = <&qusb2p_hstx_trim>; + nvmem-cell-names = "tune2_hstx_trim_efuse"; + };