From patchwork Thu Sep 22 08:35:15 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Crystal Wood X-Patchwork-Id: 673211 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sfqZJ4CSLz9ryn for ; Thu, 22 Sep 2016 18:35:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754184AbcIVIfe (ORCPT ); Thu, 22 Sep 2016 04:35:34 -0400 Received: from host.buserror.net ([209.198.135.123]:54366 "EHLO host.buserror.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755952AbcIVIfd (ORCPT ); Thu, 22 Sep 2016 04:35:33 -0400 Received: from c-75-72-173-242.hsd1.mn.comcast.net ([75.72.173.242] helo=snotra.am.freescale.net) by host.buserror.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1bmzTY-0002CR-In; Thu, 22 Sep 2016 03:35:26 -0500 From: Scott Wood To: Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland Cc: Shawn Guo , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, stuart.yoder@nxp.com, Scott Wood Date: Thu, 22 Sep 2016 03:35:15 -0500 Message-Id: <1474533318-7796-1-git-send-email-oss@buserror.net> X-Mailer: git-send-email 2.7.4 X-SA-Exim-Connect-IP: 75.72.173.242 X-SA-Exim-Mail-From: oss@buserror.net X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on host.buserror.net X-Spam-Level: X-Spam-Status: No, score=-16.0 required=5.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham autolearn_force=no version=3.4.0 X-Spam-Report: * -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP * -15 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] Subject: [PATCH v6 1/4] arm64: arch_timer: Add device tree binding for A-008585 erratum X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:57:07 +0000) X-SA-Exim-Scanned: Yes (on host.buserror.net) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Scott Wood Acked-by: Rob Herring Acked-by: Marc Zyngier Acked-by: Russell King Acked-by: Marc Zyngier Acked-by: Marc Zyngier Acked-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index e774128..ef5fbe9 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -25,6 +25,12 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +- fsl,erratum-a008585 : A boolean property. Indicates the presence of + QorIQ erratum A-008585, which says that reading the counter is + unreliable unless the same value is returned by back-to-back reads. + This also affects writes to the tval register, due to the implicit + counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize