From patchwork Wed Aug 17 05:18:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 659900 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sDcyN6vqbz9t0F for ; Wed, 17 Aug 2016 15:21:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753767AbcHQFUI (ORCPT ); Wed, 17 Aug 2016 01:20:08 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:54461 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752094AbcHQFUD (ORCPT ); Wed, 17 Aug 2016 01:20:03 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4DF2B61D02; Wed, 17 Aug 2016 05:19:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id BA40B61C12; Wed, 17 Aug 2016 05:19:10 +0000 (UTC) From: Rajendra Nayak To: andy.gross@linaro.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rajendra Nayak Subject: [PATCH v3 2/5] arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes Date: Wed, 17 Aug 2016 10:48:45 +0530 Message-Id: <1471411128-4002-3-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1471411128-4002-1-git-send-email-rnayak@codeaurora.org> References: <1471411128-4002-1-git-send-email-rnayak@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TSENS is part of GCC, hence add TSENS properties as part of GCC node. Also add thermal zones and qfprom nodes. Update GCC bindings doc to mention the possibility of optional TSENS properties that can be part of GCC node. Acked-by: Eduardo Valentin Acked-by: Rob Herring Signed-off-by: Rajendra Nayak --- .../devicetree/bindings/clock/qcom,gcc.txt | 16 ++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 103 +++++++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 9a60fde..ea893cb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -22,6 +22,11 @@ Required properties : Optional properties : - #power-domain-cells : shall contain 1 +- Qualcomm TSENS (thermal sensor device) on some devices can +be part of GCC and hence the TSENS properties can also be +part of the GCC/clock-controller node. +For more details on the TSENS properties please refer +Documentation/devicetree/bindings/thermal/qcom-tsens.txt Example: clock-controller@900000 { @@ -31,3 +36,14 @@ Example: #reset-cells = <1>; #power-domain-cells = <1>; }; + +Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 74a9b6c..0313da3 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -86,6 +86,92 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 7>; + coefficients = <1199 0>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 8>; + coefficients = <1132 0>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 9>; + coefficients = <1199 0>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 10>; + coefficients = <1132 0>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; @@ -611,11 +697,28 @@ }; }; + qfprom: qfprom@700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib { + reg = <0x414 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064"; reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #reset-cells = <1>; + #thermal-sensor-cells = <1>; }; lcc: clock-controller@28000000 {