From patchwork Wed Jun 22 15:01:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 639230 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZSVw1c52z9t1H for ; Thu, 23 Jun 2016 01:02:16 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=SFXzyCAK; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751601AbcFVPCI (ORCPT ); Wed, 22 Jun 2016 11:02:08 -0400 Received: from mail-io0-f173.google.com ([209.85.223.173]:33957 "EHLO mail-io0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751146AbcFVPCH (ORCPT ); Wed, 22 Jun 2016 11:02:07 -0400 Received: by mail-io0-f173.google.com with SMTP id g13so39563810ioj.1 for ; Wed, 22 Jun 2016 08:01:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=DUSKj2kEl11Gv7uylkyyXmKH/0qS1NZmr/6FO2MMxco=; b=SFXzyCAKfGUeR+RTMuXvwUpY45AlKoObH9jevxngrHs/Av92TAiJ9J8KwpRB0O9A0u eskxYwDfnsOGQWUdR+mKfCrx3aAnk1toDp33lOcf4XYICRgA7Kjmvd+qAX95Z8gUFpLJ MwHFrJCUDfvMSdZQ6zUGwqREKU0vsMsdcmpgM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=DUSKj2kEl11Gv7uylkyyXmKH/0qS1NZmr/6FO2MMxco=; b=Bb2iejPRbMF/b1aWsfaeYSp6IiTXpHG49GDl7ZCM2lYXgNX558x2mvCzWk7+SFXA23 hs8aekB1E9n9j6dxD0rKDVUnhLrLukYRfYkU40vomD+POlm2hkx+dwCK+s8LeK3wpzzS ePKORNnSKoqGR68w8naNCyZR6R8WFJGblrH65UspZoa7egx/Fn0zcmF1aKRvZqLZ7KOw gQGJ7HnYBzpGyDMKCkyvwz7pBcSdKSN+N6FIV6rNh82kzg4IECgg8ML0/FSVk0nRRVBN 9z+WdYDPTpBsQWYWZMCxc880pJggfuKdjTmE8WcVxTSVYunBiNicdV1/z/w7Jfln31SO hnNg== X-Gm-Message-State: ALyK8tKm8H68tfrxY3G8oRaMAIlj8Te35U2T9+dLfBoQZ+SFYa6U3cqv8TQFj7QZCjIycDDC X-Received: by 10.107.3.143 with SMTP id e15mr42607013ioi.17.1466607666208; Wed, 22 Jun 2016 08:01:06 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id q137sm3996672itb.11.2016.06.22.08.01.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jun 2016 08:01:05 -0700 (PDT) From: Mathieu Poirier To: robh+dt@kernel.org, mark.rutland@arm.com Cc: Suzuki.Poulose@arm.com, sudeep.holla@arm.com, olof@lixom.net, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V2] coresight: document binding acronyms Date: Wed, 22 Jun 2016 09:01:03 -0600 Message-Id: <1466607663-22599-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It can be hard for people not familiar with the CoreSight IP blocks to make sense of the acronyms found in the current bindings. As such this patch expands each acronym in the hope of providing a better description of the IP block they represent. Signed-off-by: Mathieu Poirier Acked-by: Sudeep Holla Reviewed-by: Suzuki K Poulose --- .../devicetree/bindings/arm/coresight.txt | 35 +++++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) Changes since V1: - Expanded ETB, ETF and ETR acronyms. - Added note about using the same binding for all 3 modes (ETB, ETF, ETR). diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 93147c0c8a0e..fcbae6a5e6c1 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -12,14 +12,33 @@ its hardware characteristcs. * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - - "arm,coresight-etb10", "arm,primecell"; - - "arm,coresight-tpiu", "arm,primecell"; - - "arm,coresight-tmc", "arm,primecell"; - - "arm,coresight-funnel", "arm,primecell"; - - "arm,coresight-etm3x", "arm,primecell"; - - "arm,coresight-etm4x", "arm,primecell"; - - "qcom,coresight-replicator1x", "arm,primecell"; - - "arm,coresight-stm", "arm,primecell"; [1] + - Embedded Trace Buffer (version 1.0): + "arm,coresight-etb10", "arm,primecell"; + + - Trace Port Interface Unit: + "arm,coresight-tpiu", "arm,primecell"; + + - Trace Memory Controller, used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) + configuration. The configuration mode (ETB, ETF, ETR) is + discovered at boot time when the device is probed. + "arm,coresight-tmc", "arm,primecell"; + + - Trace Funnel: + "arm,coresight-funnel", "arm,primecell"; + + - Embedded Trace Macrocell (version 3.x) and + Program Flow Trace Macrocell: + "arm,coresight-etm3x", "arm,primecell"; + + - Embedded Trace Macrocell (version 4.x): + "arm,coresight-etm4x", "arm,primecell"; + + - Qualcomm Configurable Replicator (version 1.x): + "qcom,coresight-replicator1x", "arm,primecell"; + + - System Trace Macrocell: + "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component.