From patchwork Tue Jun 21 18:41:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 638817 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rYxQv0rCVz9s9W for ; Wed, 22 Jun 2016 04:41:59 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=RytCxM5q; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752910AbcFUSlb (ORCPT ); Tue, 21 Jun 2016 14:41:31 -0400 Received: from mail-it0-f52.google.com ([209.85.214.52]:35371 "EHLO mail-it0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752327AbcFUSla (ORCPT ); Tue, 21 Jun 2016 14:41:30 -0400 Received: by mail-it0-f52.google.com with SMTP id g127so25762201ith.0 for ; Tue, 21 Jun 2016 11:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=rEVi+XcLE15tzGoW+Sa3VvMa8EU0tqfTbAiuyRRWyYU=; b=RytCxM5qLuN51il4f0vT0m/8LzifmyBNKp2IrVRdkZAZRHIbhA/9XtED9nOl99r+J9 lzaf6fTicmceppC+9p55CbwxHZ1n7bYnOb5eAQUjKlehUxmeR8ruUkB0GEmO/YJ3Dzh5 L7gXY8X1+zTij9x3C8HBEYOiIx2S1FGbER74k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rEVi+XcLE15tzGoW+Sa3VvMa8EU0tqfTbAiuyRRWyYU=; b=S8yhUVN/haFjA4irmyfcYp+lieOywacB+6NumYIhUc94cQfeoJD+HjnrWIFx7G7ltD knb8TSHX7JzzfOgZIYtYzI/rOGYU9Ni9u7Jy6SkHm/3c7RiqYiqw5Lv+Fmbzie3IV5Us bKsE5fos6NbCaHS1+1nMVBJlEpN7wa6aCU4bNrYSPr1tEKsf/ANWD4E01HhNN6oGq/Se MvvQhmrgZ9xPsD0owt+JSU0BcOqAK3spfgjjw/bDYjFK3HYIjZGZwG8VVMZQWfF1dYbM qgsFm8SQViJJna97R/n9ZROlwM4OsSz8ZJe6kpXIudNxhgOnWvYQY5BnqTLg1a8kUO/D DT/Q== X-Gm-Message-State: ALyK8tLxVA0KKk7VNbZ7/yPDKCVoPdIx30s/U4ISuBeuukx8iD8ofY37McGo26Jcq6I6SieF X-Received: by 10.36.104.206 with SMTP id v197mr8448499itb.54.1466534489407; Tue, 21 Jun 2016 11:41:29 -0700 (PDT) Received: from t430.cg.shawcable.net (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id d15sm1922419itb.12.2016.06.21.11.41.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Jun 2016 11:41:28 -0700 (PDT) From: Mathieu Poirier To: robh+dt@kernel.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, sudeep.holla@arm.com, suzuki.poulose@arm.com, olof@lixom.net Subject: [PATCH] coresight: document binding acronyms Date: Tue, 21 Jun 2016 12:41:26 -0600 Message-Id: <1466534486-22422-1-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It can be hard for people not familiar with the CoreSight IP blocks to make sense of the acronyms found in the current bindings. As such this patch expands each acronym in the hope of providing a better description of the IP block they represent. Signed-off-by: Mathieu Poirier --- .../devicetree/bindings/arm/coresight.txt | 32 ++++++++++++++++------ 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index 93147c0c8a0e..c73a7f773998 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -12,14 +12,30 @@ its hardware characteristcs. * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - - "arm,coresight-etb10", "arm,primecell"; - - "arm,coresight-tpiu", "arm,primecell"; - - "arm,coresight-tmc", "arm,primecell"; - - "arm,coresight-funnel", "arm,primecell"; - - "arm,coresight-etm3x", "arm,primecell"; - - "arm,coresight-etm4x", "arm,primecell"; - - "qcom,coresight-replicator1x", "arm,primecell"; - - "arm,coresight-stm", "arm,primecell"; [1] + - Embedded Trace Buffer (version 1.0): + "arm,coresight-etb10", "arm,primecell"; + + - Trace Port Interface Unit: + "arm,coresight-tpiu", "arm,primecell"; + + - Trace Memory Controller (ETB, ETF, ETR): + "arm,coresight-tmc", "arm,primecell"; + + - Trace Funnel: + "arm,coresight-funnel", "arm,primecell"; + + - Embedded Trace Macrocell (version 3.x) and + Program Flow Trace Macrocell: + "arm,coresight-etm3x", "arm,primecell"; + + - Embedded Trace Macrocell (version 4.x): + "arm,coresight-etm4x", "arm,primecell"; + + - Qualcomm Configurable Replicator (version 1.x): + "qcom,coresight-replicator1x", "arm,primecell"; + + - System Trace Macrocell: + "arm,coresight-stm", "arm,primecell"; [1] * reg: physical base address and length of the register set(s) of the component.