From patchwork Mon May 9 12:32:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 619875 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r3MHP6dLRz9t3k for ; Mon, 9 May 2016 22:33:21 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=jms.id.au header.i=@jms.id.au header.b=kmQeRxkZ; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752963AbcEIMdV (ORCPT ); Mon, 9 May 2016 08:33:21 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:36721 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751565AbcEIMdU (ORCPT ); Mon, 9 May 2016 08:33:20 -0400 Received: by mail-pa0-f51.google.com with SMTP id bt5so71881446pac.3 for ; Mon, 09 May 2016 05:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N+zMpIVceuCoMwuorig/SYbrzwvYBjLl46SoVmdMcE4=; b=kmQeRxkZA/AK8vfQvdODNoGmLLkIzk+4s8cbyVC8NoM3fRJeGm0mG8f+V7i36rko2o /nZcdKeG3Fw6Vl64VGzN05+J2igbbAm2SKzG8PVzB74nPkCpSd0u4d8tTKUKSvdBryMl c0RJGI3v6sIvgvkfEtWef2l1xIdIA/FhpBSLo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N+zMpIVceuCoMwuorig/SYbrzwvYBjLl46SoVmdMcE4=; b=Xi16VhrsXLT/OzXuZhyFV+qYcUS/zFKWsqerw9o4NfM1lDYYiYuRvnsEUdU4zNVpPA mBd9D4TfJ8fHoLoyPJr03Kx24axDe2Qa1+6TcKeg7SSuzit4rrW8aBo9U3lqpqqw1/gN AP1BlUrDGIbNCQyH/wzAsC44BnXyoexnM6y9sojWmZ61lQI56gNzxJM/aAh2Jkkuuk+A 9Y/wcYykbcra4sOEV45ufw+B4ht4cs6zsu88kCFDk6jHfvPD82LjCHE6VHr8wYLu99Zz kfkjRfT/1wJyjMg2GLZ5oZUmIjbbHY1iwnfoQ/5i4QjPk6UVTy6R7skCvIFKsvmZD72G c9WA== X-Gm-Message-State: AOPr4FWpPQgfASPtZ8xHwI8tQibtCZYYjU5sUqBnelBX30H1yV8ShFROaiavZOUjpYSfMA== X-Received: by 10.66.167.40 with SMTP id zl8mr50405285pab.8.1462797199970; Mon, 09 May 2016 05:33:19 -0700 (PDT) Received: from icarus.au.ibm.com ([2403:480:11:10:3400:b218:cbe9:48cb]) by smtp.gmail.com with ESMTPSA id e2sm34452101pfd.20.2016.05.09.05.33.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 May 2016 05:33:19 -0700 (PDT) From: Joel Stanley To: daniel.lezcano@linaro.org, tglx@linutronix.de, jonas.jensen@gmail.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jk@ozlabs.org, benh@kernel.crashing.org, arnd@arndb.de Subject: [PATCH 4/4] drivers/clocksource/moxart: Add Aspeed support Date: Mon, 9 May 2016 22:02:49 +0930 Message-Id: <1462797169-14512-5-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1462797169-14512-1-git-send-email-joel@jms.id.au> References: <1462797169-14512-1-git-send-email-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Aspeed SoC has timer IP with a very similar register layout to the moxart timer. This patch adds support for the fourth and fifth gen aspeed SoCs, and has been tested on the ast2400 and ast2500. Signed-off-by: Joel Stanley Acked-by: Rob Herring --- .../bindings/timer/moxa,moxart-timer.txt | 4 ++- drivers/clocksource/moxart_timer.c | 32 ++++++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt index da2d510cae47..e207c11630af 100644 --- a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt +++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt @@ -2,7 +2,9 @@ MOXA ART timer Required properties: -- compatible : Must be "moxa,moxart-timer" +- compatible : Must be one of: + - "moxa,moxart-timer" + - "aspeed,ast2400-timer" - reg : Should contain registers location and length - interrupts : Should contain the timer interrupt number - clocks : Should contain phandle for the clock that drives the counter diff --git a/drivers/clocksource/moxart_timer.c b/drivers/clocksource/moxart_timer.c index d17e3eface87..83ffa2727699 100644 --- a/drivers/clocksource/moxart_timer.c +++ b/drivers/clocksource/moxart_timer.c @@ -56,6 +56,23 @@ #define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE) #define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE) +/* + * The ASpeed variant of the IP block has a different layout + * for the control register + */ +#define ASPEED_CR_1_ENABLE BIT(0) +#define ASPEED_CR_1_CLOCK BIT(1) +#define ASPEED_CR_1_INT BIT(2) +#define ASPEED_CR_2_ENABLE BIT(4) +#define ASPEED_CR_2_CLOCK BIT(5) +#define ASPEED_CR_2_INT BIT(6) +#define ASPEED_CR_3_ENABLE BIT(8) +#define ASPEED_CR_3_CLOCK BIT(9) +#define ASPEED_CR_3_INT BIT(10) + +#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE) +#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE) + struct moxart_timer { void __iomem *base; unsigned int t1_disable_val; @@ -159,6 +176,9 @@ static void __init moxart_timer_init(struct device_node *node) if (of_device_is_compatible(node, "moxa,moxart-timer")) { timer->t1_enable_val = MOXART_TIMER1_ENABLE; timer->t1_disable_val = MOXART_TIMER1_DISABLE; + } else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) { + timer->t1_enable_val = ASPEED_TIMER1_ENABLE; + timer->t1_disable_val = ASPEED_TIMER1_DISABLE; } else panic("%s: unknown platform\n", node->full_name); @@ -189,6 +209,17 @@ static void __init moxart_timer_init(struct device_node *node) if (ret) panic("%s: setup_irq failed\n", node->full_name); + /* Clear match registers */ + writel(0, timer->base + TIMER1_BASE + REG_MATCH1); + writel(0, timer->base + TIMER1_BASE + REG_MATCH2); + writel(0, timer->base + TIMER2_BASE + REG_MATCH1); + writel(0, timer->base + TIMER2_BASE + REG_MATCH2); + + /* + * Start timer 2 rolling as our main wall clock source, keep timer 1 + * disabled + */ + writel(0, timer->base + TIMER_CR); writel(~0, timer->base + TIMER2_BASE + REG_LOAD); writel(timer->t1_disable_val, timer->base + TIMER_CR); @@ -201,3 +232,4 @@ static void __init moxart_timer_init(struct device_node *node) clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe); } CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init); +CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init);