From patchwork Wed May 4 22:50:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Gross X-Patchwork-Id: 618702 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r0YDS2VJZz9t4k for ; Thu, 5 May 2016 08:51:04 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=gm/6s2gm; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755202AbcEDWu6 (ORCPT ); Wed, 4 May 2016 18:50:58 -0400 Received: from mail-oi0-f41.google.com ([209.85.218.41]:35129 "EHLO mail-oi0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754903AbcEDWu5 (ORCPT ); Wed, 4 May 2016 18:50:57 -0400 Received: by mail-oi0-f41.google.com with SMTP id x19so83696242oix.2 for ; Wed, 04 May 2016 15:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=x0nHf3+G9wU4Y9DiWSWFrKpQaOL1daJNZMyNEEPg1kE=; b=gm/6s2gmadwfcf6Bt+T5qPIprkB79CUxGD0ufXW3MypK+VcRzrfJ4l+FgIeOe/Ot6V Hkyqk7ARrOGWHDT43AS8PtFwV/l+rkvWe0k/TdbwUWaAn/x9WaOVaLF2qb/45B+dVL0y bQN3WN8sePynIOkSLG0gBp2iRulLf4Bq8ITbE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=x0nHf3+G9wU4Y9DiWSWFrKpQaOL1daJNZMyNEEPg1kE=; b=MJFACkXKk6aVeOgP3jnkXElSGCvV6F7TkJDVipbmpvj17sw19gCJwJvgNJCj6f9Yxj kHQ0rclJTJvJ7Pfpi+I9/LifTGQDETQI/syH6TbnuqXdgxqSPDf7/Im8dSd6zVBxtsIC 0h9MZd9Td56cLidsMxiU3ziGq2nECIVb+h1/5zIqmlIGXlGbIN5OmHPAitUNZsWvrAaU +88DnjsQeFo+MKLiVsxENiFK2p0gPs8AhSMfdUKaQvnLVMup7vYqhsqnmDUYvnYgsj/P rPn3vIOB+zjDdnRR2F6vzE2aTaXOPLk9YaSXEjsOEoOnwlMdQfP1qvAziv4yS1dkxW6W jrJg== X-Gm-Message-State: AOPr4FXMbJQ7GkAUdOteir4OdaaLDil1wAL3u4/atia1EQKwP4fw9i5FQsD0OTt9AB8G/pBW X-Received: by 10.202.74.10 with SMTP id x10mr4930099oia.157.1462402251548; Wed, 04 May 2016 15:50:51 -0700 (PDT) Received: from localhost ([2602:306:c558:19b0:7540:9cc9:16d9:58a9]) by smtp.gmail.com with ESMTPSA id n106sm2170708ota.22.2016.05.04.15.50.50 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Wed, 04 May 2016 15:50:51 -0700 (PDT) From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stephen Boyd , Bjorn Andersson , jilai wang , devicetree@vger.kernel.org, Andy Gross Subject: [Patch v3 1/8] dt/bindings: firmware: Add Qualcomm SCM binding Date: Wed, 4 May 2016 17:50:38 -0500 Message-Id: <1462402245-18295-2-git-send-email-andy.gross@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462402245-18295-1-git-send-email-andy.gross@linaro.org> References: <1462402245-18295-1-git-send-email-andy.gross@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the device tree support for the Qualcomm SCM firmware. Signed-off-by: Andy Gross --- .../devicetree/bindings/firmware/qcom,scm.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/qcom,scm.txt diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt new file mode 100644 index 0000000..ee7cd12 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -0,0 +1,26 @@ +QCOM Secure Channel Manager (SCM) + +Qualcomm processors include an interface to communicate to the secure firmware. +This interface allows for clients to request different types of actions. These +can include CPU power up/down, HDCP requests, loading of firmware, and other +assorted actions. + +Required properties: +- compatible: must contain one of the following: + * "qcom,scm-a-family" for A family Qualcomm processors (APQ8064, MSM8960, etc) + * "qcom,scm" for B family and later processors (MSM8916, APQ8084, MSM8974, etc) +- clocks: One to three clocks may be required based on compatible. + * Only core clock required for "qcom,scm-apq8064" + * Core, iface, and bus clocks required for "qcom,scm" +- clock-names: Must contain "core" for the core clock, "iface" for the interface + clock and "bus" for the bus clock per the requirements of the compatible. + +Example for MSM8916: + + firmware { + scm { + compatible = "qcom,scm"; + clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + }; + };