From patchwork Mon Mar 28 09:23:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 602417 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qYT4T2msxz9s9k for ; Mon, 28 Mar 2016 20:24:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754894AbcC1JXx (ORCPT ); Mon, 28 Mar 2016 05:23:53 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2328 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754859AbcC1JXv (ORCPT ); Mon, 28 Mar 2016 05:23:51 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 28 Mar 2016 02:23:36 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 28 Mar 2016 02:22:06 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 28 Mar 2016 02:22:06 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.406.0; Mon, 28 Mar 2016 02:23:49 -0700 From: Alexandre Courbot To: Stephen Warren , Thierry Reding CC: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH v3 2/5] dt-bindings: gk20a: Document iommus property Date: Mon, 28 Mar 2016 18:23:01 +0900 Message-ID: <1459156984-32644-3-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1459156984-32644-1-git-send-email-acourbot@nvidia.com> References: <1459156984-32644-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GK20A can optionally make use of an IOMMU. Signed-off-by: Alexandre Courbot Acked-by: Rob Herring --- Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt index 914f0ff4020e..1e3748337319 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt @@ -24,6 +24,9 @@ Required properties: - reset-names: Must include the following entries: - gpu +Optional properties: +- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. + Example: gpu@0,57000000 { @@ -39,5 +42,6 @@ Example: clock-names = "gpu", "pwr"; resets = <&tegra_car 184>; reset-names = "gpu"; + iommus = <&mc TEGRA_SWGROUP_GPU>; status = "disabled"; };