From patchwork Sun Mar 27 09:26:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 602330 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qXs9w5NVnz9sC3 for ; Sun, 27 Mar 2016 20:26:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753592AbcC0J0k (ORCPT ); Sun, 27 Mar 2016 05:26:40 -0400 Received: from down.free-electrons.com ([37.187.137.238]:38706 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753191AbcC0J0j (ORCPT ); Sun, 27 Mar 2016 05:26:39 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id D181F605; Sun, 27 Mar 2016 11:26:36 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (unknown [37.205.56.247]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5EEE9629; Sun, 27 Mar 2016 11:26:26 +0200 (CEST) From: Thomas Petazzoni To: Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring , Ian Campbell , Pawel Moll , Mark Rutland , Kumar Gala Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Nadav Haklai , Lior Amsalem , Hanna Hawa , linux-arm-kernel@lists.infradead.org, Thomas Petazzoni Subject: [PATCH v4 2/5] dt-bindings: arm: add DT binding for Marvell AP806 system controller Date: Sun, 27 Mar 2016 11:26:14 +0200 Message-Id: <1459070777-18049-3-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1459070777-18049-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1459070777-18049-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This commit adds the Device Tree binding documentation for the system controller found in Marvell AP806 HW block, which is one of the core HW blocks of the 64-bits Marvell Armada 7K/8K family. Signed-off-by: Thomas Petazzoni Acked-by: Rob Herring --- .../arm/marvell/ap806-system-controller.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt new file mode 100644 index 0000000..8968371 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt @@ -0,0 +1,35 @@ +Marvell Armada AP806 System Controller +====================================== + +The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K +SoCs. It contains a system controller, which provides a number +registers giving access to numerous features: clocks, pin-muxing and +many other SoC configuration items. This DT binding allows to describe +this system controller. + +The Device Tree node representing the AP806 system controller provides +a number of clocks: + + - 0: clock of CPU cluster 0 + - 1: clock of CPU cluster 1 + - 2: fixed PLL at 1200 Mhz + - 3: MSS clock, derived from the fixed PLL + +Required properties: + + - compatible: must be: + "marvell,ap806-system-controller", "syscon" + - reg: register area of the AP806 system controller + - #clock-cells: must be set to 1 + - clock-output-names: must be defined to: + "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss" + +Example: + + syscon: system-controller@6f4000 { + compatible = "marvell,ap806-system-controller", "syscon"; + #clock-cells = <1>; + clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1", + "ap-fixed", "ap-mss"; + reg = <0x6f4000 0x1000>; + };